DS2182AQN View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

DS2182AQN

T1 Line Monitor Chip

Maxim Integrated 

DS2182A T1 Line Monitor Chip

SERIAL PORT INTERFACE

The port pins of the DS2182A serve as a microprocessor/microcontroller-compatible serial port. Eleven on-board

registers allow the user to update operational characteristics and monitor device status through a host controller,

minimizing hardware interfaces. The port on the DS2182A can be read from or written to at any time. Serial port

reads and writes are independent of T1 line timing signals RCLK, RPOS, and RNEG. However, RCLK is needed to

clear RSR1 and RSR2 after reads.

ADDRESS/COMMAND

Reading or writing the control, configuration, or status registers requires writing one address/command byte prior to

transferring register data. The first bit written (LSB) of the address/command word specifies register read or write.

The following four bits identify the register address. The next two bits are reserved and must be set to 0 for proper

operation. The last bit of the address/ command word enables burst mode when set. The burst mode causes all

registers to be consecutively read or written to. Data is read and written to the DS2182A LSB first.

CHIP SELECT AND CLOCK CONTROL

All data transfers are initiated by driving the CS input low. Input data is latched on the rising edge of SCLK and

must be valid during the previous low period of SCLK to prevent momentary corruption of register data during

writes. Data is output on the falling edge of SCLK and held to the next falling edge. All data transfers are

terminated if the CS input transitions high. Port control logic is disabled and SDO is tri-stated when CS is high.

DATA I/O

Following the eight SCLK cycles that input an address/command byte to write, a data byte is strobed into the

addressed register on the rising edge of the next eight SCLK cycles. Following an address/command word to read,

contents of the selected register are output on the falling edges of the next eight SCLK cycles. The SDO pin is tri-

stated during device write and can be connected to SDI in applications where the host processor has a

bidirectional I/O pin.

BURST MODE

The burst mode allows all on-board registers to be consecutively written to or read by the host processor. A burst

read is used to poll all registers. RSR1 and RSR2 contents are unaffected. This feature minimizes device

initialization time on system power-up or reset. Burst mode is initiated when ACB.7 is set and the address is 0000.

A burst is terminated by a low-high transition on CS.

ACB: Address Command Byte

MSB

BM

—

—

ADD3

ADD2

ADD1

ADD0

LSB

R/W

NAME

BM

—

—

ADD3

ADD0

R/W

POSITION

ACB.7

ACB.6

ACB.5

ACB.4

ACB.1

ACB.0

FUNCTION

Burst Mode. If set (and register address is 0000), burst read or write is

enabled.

Reserved; must be 0 for operation

Reserved; must be 0 for operation

MSB of register address

LSB of register address

Read/Write Select

0 = write addressed register

1 = read addressed register

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