DS2450 View Datasheet(PDF) - Maxim Integrated
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DS2450 Datasheet PDF : 25 Pages
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DS2450
the comparison. Each A/D conversion is initiated by the bus master. A channel not used as analog input
can serve as a digital open-drain output. After disabling the input the bus master can directly switch on or
off the open-drain transistor at the selected channel. All device settings are stored in SRAM and kept
non-volatile while the device gets power either through the 1-Wire bus or through its VCC pin. After
powering up, a power-on reset flag signals the bus master the need to restore the device settings before
the regular operation can resume. All device registers and conversion read-out registers are organized as
three 8-byte memory pages similar to the Status Memory of a DS2505/6 device. An on-chip CRC16
generator protects the communication against transmission errors when reading through the end of a
memory page as well as when writing individual bytes.
OVERVIEW
The block diagram in Figure 1 shows the major function blocks of the device. The DS2450 contains a
factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-
bit family code (20H). The 64-bit ROM portion of the DS2450 not only creates an absolutely unique
electronic identification for the device itself but also is a means to locate and address the device in order
to exercise its control functions.
The device gets its power either from the 1-Wire bus or through its VCC pin. Without a VCC supply the
device stores energy on an internal capacitor during periods where the signal line is high and continues to
operate off of this “parasite” power source during the low times of the 1-Wire line until it returns to high
to replenish the parasite (capacitor) supply. This, however, provides sufficient energy only for
communication. To perform an A/D conversion a strong pullup of the 1-Wire bus to 5V or a VCC supply
is required.
DS2450 BLOCK DIAGRAM Figure 1
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