EL7556D View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
EL7556D Datasheet PDF : 11 Pages
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EL7556D
pulse by pulse current limiting, rapid response to line variation
and good load step response.
The heart of the controller is a triple-input direct summing
comparator which sums voltage feedback, current feedback
and slope compensating ramp signals together. Slope
compensation is required to prevent system instability which
occurs in current-mode topologies operating at duty-cycles
greater than 50% and is also used to define the open-loop gain
of the overall system. The compensation ramp amplitude is
user adjustable and is set using a single external capacitor
(CSLOPE). Each comparator input is weighted and determines
the load and line regulation characteristics of the system.
Current feedback is measured by sensing the inductor current
flowing through the high-side switch whenever it is conducting.
At the beginning of each oscillator period the high-side NMOS
switch is turned on and CSLOPE ramps positively from its reset
state (VREF potential). The comparator inputs are gated off for
a minimum period of time (LEB) after the high-side switch is
turned on to allow the system to settle. The Leading Edge
Blanking (LEB) period prevents the detection of erroneous
voltages at the comparator inputs due to switching noise.
When programming low regulator output voltages the LEB
delay will limit the maximum operating frequency of the circuit
since the LEB will result in a minimum duty-cycle regardless of
the PWM error voltage. This relationship is shown in the
performance curves. If the inductor current exceeds the
maximum current limit (ILMAX), a secondary over-current
comparator will terminate the high-side switch. If ILMAX has not
been reached, the regulator output voltage is then compared to
the reference voltage VREF. The resultant error voltage is
summed with the current feedback and slope compensation
ramp. The high-side switch remains on until all three
comparator inputs have summed to zero, at which time the
high-side switch is turned off and the low-side switch is turned
on. In order to eliminate cross-conduction of the high-side and
low-side switches a 10ns break-before-make delay is
incorporated in the switch driver circuitry. In the continuous
mode of operation the low-side switch will remain on until the
end of the oscillator period. In order to improve the low current
efficiency of the EL7556D, a zero-crossing comparator senses
when the inductor transitions through zero. Turning off the low-
side switch at zero inductor current prevents forward
conduction through the internal clamping diodes (LX to VSSP)
when the low-side switch turns off, reducing power dissipation.
The output enable (OUTEN) input allows the regulator output
to be disabled by an external logic control signal.
Output Voltage Mode Select
The VCC2DET multiplexes the FB1 and FB2 pins to the PWM
controller. A logic 1 on VCC2DET selects the FB2 input and
forces the output voltage to the internally programmed value of
3.50V. A logic zero on VCC2DET selects FB1 and allows the
output to be programmed from 1.0 to 3.8V. In general:
VOUT
=
1
V
1
+
RR-----34-
Volt
However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and loop-
gain are changed. This is shown in the performance curves.
(The output voltage is factory trimmed to minimize error at a
2.50V output). A 2uA pull-up current from FB1 to VIN forces
VOUT to GND in the event that FB1 is not used and the
VCC2DET is inadvertently toggled between the internal and
external feedback mode of operation.
NMOS Power FETs and Drive Circuitry
The EL7556D integrates low resistance (25m) NMOS FETS
to achieve high efficiency at 6A. Gate drive for both the high-
side and low-side switches is derived through a charge pump
consisting of the CP pin and external components D1-D3 and
C5-C6. The CP output is a low resistance inverter driven at
one-half the oscillator frequency. This is used in conjunction
with D2-D3 to generate a 7.5V (typical) voltage on the C2V pin
which provides gate drive to the low-side NMOS switch and
associated level shifter. In order to use an NMOS switch for the
high-side drive it is necessary to drive the gate voltage above
the source voltage (LX). This is accomplished by boot-
strapping the VHI pin above the C2V voltage with capacitor C6
and diode D1. When the low-side switch is turned on the LX
voltage is close to GND potential and capacitor C6 is charged
through diodes D1-D3 to approximately 6.9V. At the beginning
of the next cycle the high side switch turns on and the LX pin
begins to rise from GND to VDD potential. As the LX pin rises
the positive plate of capacitor C6 follows and eventually
reaches a value of approximately 11.2V, for VDD=5V. This
voltage is then level shifted and used to drive the gate of the
high-side FET, via the VHI pin.
Reference
A 1% temperature compensated band gap reference is
integrated in the EL7556D. The external CREF capacitor acts
as the dominant pole of the amplifier and can be increased in
size to maximize transient noise rejection. A value of 0.1uF is
recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 96%.
Operating frequency can be adjusted through the COSC pin or
can be driven by an external clock source. If the oscillator is
driven by an external source, care must be taken in the
selection of CSLOPE. Since the COSC and CSLOPE values
determine the open loop gain of the system, changes to COSC
require corresponding changes to CSLOPEin order to maintain
a constant gain ratio. The recommended ratio of COSC to
CSLOPE is 1.5:1
Temperature Sensor
An internal temperature sensor continuously monitors die
temperature. In the event that die temperature exceeds the
thermal trip-point, the OT pin will output a logic 0. The upper
and lower trip points are set to 135°C and 100°C, respectively.
To enable thermal shutdown this pin should be tied directly to
FN7339 Rev 1.00
August 1, 2005
Page 10 of 11
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