MGA-83563 View Datasheet(PDF) - Avago Technologies
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MGA-83563 Datasheet PDF : 22 Pages
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The channel-to-case thermal resistance (Tch-c) from
the table of Absolute Maximum Ratings is 175°C/watt.
Note that the meaning of “case” for packages such
as the SOT-363 is defined as the interface between
the package pins and the mounting surface, i.e., at
the PCB pads. The temperature rise from the mount-
ing surface to the MMIC channel is then calculated as
0.264 watt * 175°C/watt, or 46°C.
Operating life tests [1] for the MGA-83563 have estab-
lished that a MTTF of 106 hours will be met for channel
temperatures ≤ 150°C. To achieve the 106 hour MTTF
goal, the circuit to which the device is mounted (i.e., the
case temperature) should therefore not exceed 150° –
46°C, or 104°C.
Repeating the reliability calculation using the worst case
maximum device current of 200 mA, the DC power dis-
sipation is 552 mW. Summing the RF input and output
powers, Pdiss is 397 mW which results in a channel-to-
case temperature rise of 69°C. The maximum case tem-
perature for the MTTF goal of 106 hours is then 150°–
69°C, or 81°C.
For other MTTF goals, power dissipation, or operating
temperatures, Avago publishes reliability data sheets
based on operating life tests to enable designers to arrive
at a thermal design for their particular operating envi-
ronment. For a reliability data sheet covering the MGA-
83563, request Avago publication number 5988-9935EN,
titled "MGA-8XXXX Series Reliability Data Sheet." This
reliability data sheet covers the Avago family of PHEMT
GaAs RFICs.
Linear Amplifier Thermal Example
If the MGA-83563 is used in a linear application, the total
power dissipation is significantly higher than for the
saturated mode. The dissipated power is greater due
to higher device current (not as efficient as the satu-
rated mode) and also because no signal power is being
removed.
The maximum power dissipation for reliable linear op-
eration is calculated in the same manner as was done for
the saturated amplifier example. For linear circuits, the
RF input and output power are negligible and assumed
to be zero. All of the DC power is thus dissipated as heat.
For purposes of comparison to the saturated mode
example, this calculation will use the same MTTF goal of
106 hours and supply voltage of 3 volts. Calculations are
again made for both nominal and worst case conditions.
From the data of Figure 10, the typical 3-volt, small signal
device current for the MGA-83563 at elevated tempera-
tures is 156 mA. The total device power dissipation, Pdiss,
is then 3.0 volts * 156 mA, or 468 mW. The temperature
increment from the RFIC channel to case is 0.468 watt *
175°C/watt, or 82°C.
Commensurate with the MTTF goal of 106 hours, the
circuit to which the device is mounted should therefore
not exceed 150°– 82°C, or 68°C.
For the worst case calculation, a guard band of 40% is
added to the typical current to arrive at a maximum DC
current of 218 mA. The Pdiss is 655 mW and the channel-
to-case temperature rise is 115°C. The maximum case
temperature for worst case current condition is 35°C.
A case temperature of 68°C for nominal operation, or
35°C in the worst case, is unacceptably low for most ap-
plications. In order to use the MGA-83562 reliably for
linear applications, the Pdiss must be lowered by reduc-
ing the supply voltage.
The implication on RF output power performance for
amplifiers operating with a reduced Vd is covered later in
this application note in the section subtitled “Use of the
MGA-83563 for Linear Applications”.
Design Example for 2.5 GHz
The design of a 2.5 GHz amplifier will be used to illus-
trate the approach for using the MGA-83563. The basic
design procedure outlined earlier will be used, in which
the interstage inductor (L2) is chosen first, followed by
the design of an initial small signal, output match. The
output match will then be empirically optimized for
large signal conditions after which an input match will
be added.
The printed circuit layout in Figure 21 is used as the start-
ing place. The circuit is designed for fabrication on 0.031-
inch thick FR-4 dielectric material.
Interstage Inductor L2
The first step is to choose a value for the interstage in-
ductor, L2. Referring to Figure 19, a value of 1.5 nH corre-
sponds to the design frequency of 2.5 GHz. A chip induc-
tor is chosen for L2 in this example. However, for small
inductance values such as this, the interstage inductor
could also be realized with a length of high impedance
transmission line.
The interstage inductor is bypassed with a 62 pF capaci-
tor, which has a reactance of 1 Ω at 2.5 GHz. Connecting
the supply voltage to the bypassed side of the inductor
completes the interstage part of the amplifier.
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