ISL6209 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
ISL6209 Datasheet PDF : 10 Pages
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ISL6209
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
UGATE Turn-On Propagation Delay
tPDHUGATE VVCC = 5V, Outputs Unloaded,
DELAY = VCC
10
20
30
ns
LGATE Turn-On Propagation Delay
tPDHLGATE VVCC = 5V, Outputs Unloaded,
DELAY = VCC
10
20
30
ns
OUTPUT
Upper Drive Source Resistance
RUGATE 500mA Source Current
Upper Driver Source Current (Note 5)
IUGATE VUGATE-PHASE = 2.5V
Upper Drive Sink Resistance
RUGATE 500mA Sink Current
Upper Driver Sink Current (Note 5)
IUGATE VUGATE-PHASE = 2.5V
Lower Drive Source Resistance
RLGATE 500mA Source Current
Lower Driver Source Current (Note 5)
ILGATE VLGATE = 2.5V
Lower Drive Sink Resistance
RLGATE 500mA Sink Current
Lower Driver Sink Current (Note 5)
ILGATE VLGATE = 2.5V
NOTE:
5. Guaranteed by characterization, not 100% tested in production.
-
1.0
2.5
-
2.0
-
A
-
1.0
2.5
-
2.0
-
A
-
1.0
2.5
-
2.0
-
A
-
0.4
1.0
-
4.0
-
A
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to the
gate of high-side power N-Channel MOSFET.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller. In
addition, place a 500k resistor to ground from this pin. This
allows for proper three-state operation under all start-up
conditions.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin. All signals are referenced to this node.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high quality
bypass capacitor from this pin to GND.
FN9132 Rev.2.00
Mar 23, 2007
DELAY (Pin 7 for SOIC-8, Pin 6 for QFN)
The DELAY pin sets the dead-time between gate switching for
the ISL6209. Connect a resistor to GND from this pin to adjust
the dead-time, refer to Figure 4. Tie this pin to VCC to disable
the delay circuitry. See Shoot-Through Protection section for
more detail.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a return
path for the upper gate driver.
Description
Operation
Designed for speed, the ISL6209 dual MOSFET driver controls
both high-side and low-side N-Channel FETs from one externally
provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [tPDLLGATE], the lower gate begins to fall. Typical fall
times [tFLGATE] are provided in the Electrical Specifications
section. Adaptive shoot-through circuitry monitors the LGATE
voltage and determines the upper gate delay time
[tPDHUGATE], based on how quickly the LGATE voltage drops
below 1V. This prevents both the lower and upper MOSFETs
from conducting simultaneously, or shoot-through. Once this
delay period is completed, the upper gate drive begins to rise
[tRUGATE], and the upper MOSFET turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [tPDLUGATE] is encountered before the
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