ISL6209 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
ISL6209 Datasheet PDF : 10 Pages
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ISL6209
upper gate begins to fall [tFUGATE]. Again, the adaptive shoot-
through circuitry determines the lower gate delay time
tPDHLGATE. The upper MOSFET gate-to-source voltage is
monitored, and the lower gate is allowed to rise, after the upper
MOSFET gate-to-source voltage drops below 1V. The lower
gate then rises [tRLGATE], turning on the lower MOSFET.
This driver is optimized for converters with large step down
ratio, such as those used in a mobile-computer core voltage
regulator. The lower MOSFET is usually sized much larger.
This driver is optimized for converters with large step down
compared to the upper MOSFET because the lower MOSFET
conducts for a much longer time in a switching period. The
lower gate driver is therefore sized much larger to meet this
application requirement. The 0.4 on-resistance and 4A sink
current capability enable the lower gate driver to absorb the
current injected to the lower gate through the drain-to-gate
capacitor of the lower MOSFET and prevent a shoot through
caused by the high dv/dt of the phase node.
Three-State PWM Input
A unique feature of the ISL6209 and other Intersil drivers is the
addition of a shutdown window to the PWM input. If the PWM
signal enters and remains within the shutdown window for a
set holdoff time, the output drivers are disabled and both
MOSFET gates are pulled and held low. The shutdown state is
removed when the PWM signal moves outside the shutdown
window. Otherwise, the PWM rising and falling thresholds
outlined in the ELECTRICAL SPECIFICATIONS determine
when the lower and upper gates are enabled. During start-up,
PWM should be in the three-state position (1/2 VCC) until
actively driven by the controller IC.
Shoot-Through Protection
The ISL6209 driver delivers shoot-through protection by
incorporating gate threshold monitoring and programmable
dead-time to prevent upper and lower MOSFETs from
conducting simultaneously, thereby shorting the input supply to
ground. Gate threshold monitoring ensures that one gate is
OFF before the other is allowed to turn ON.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Internal circuitry monitors the
upper MOSFET gate-to-source voltage during UGATE
turn-off. Once the upper MOSFET gate-to-source voltage has
dropped below a threshold of 1V, the LGATE is allowed to
rise.
In addition to gate threshold monitoring, a programmable delay
between MOSFET switching can be accomplished by placing a
resistor from the DELAY pin to ground. This delay allows for
maximum design flexibility over MOSFET selection. The delay
can be programmed from 5ns to 50ns. If not desired, the
DELAY pin must be tied to VCC to disable the delay circuitry.
Gate threshold monitoring is not affected by the addition or
removal of the additional dead-time. Refer to Figure 3 and
Figure 4 for more detail.
GATE A
FCCM = VCC or GND
GATE B
Adaptive Shoot-Through Protection
1V
GATE A
FCCM = RESISTOR to VCC or GND
GATE B
Adaptive Protection with Delay
tdelay = 5n - 50ns
1V
FIGURE 3. PROGRAMMABLE DEAD-TIME
4
50
45
40
35
30
tDELAY
25
20
15
10
5
0
0
50
100
150
200
250
300
RDELAY (k)
FIGURE 4. ADDITIONAL PROGRAMMED DEAD-TIME
(tDELAY) vs DELAY RESISTOR VALUE
FN9132 Rev.2.00
Mar 23, 2007
Page 6 of 10
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