ISL6209 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
ISL6209 Datasheet PDF : 10 Pages
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ISL6209
The equation governing the dead-time seen in Figure 4 is
expressed as:
TDELAY = 160 10–15 RDELAY + 6ns
The equation can be rewritten to solve for RDELAY as follows:
RDELAY = ---T----1D---6-E--0--L---A----Y-1---0-–---–--6-1---n5---s----
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage rating
above the maximum battery voltage plus 5V. The bootstrap
capacitor can be chosen from the following equation:
CBOOT ---Q--V--G--B---A-O---T-O--E---T-
where QGATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The VBOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, QGATE, of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find that
a bootstrap capacitance of at least 0.125F is required. The
next larger standard value capacitance is 0.22F. A good
quality ceramic capacitor is recommended.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
QGATE = 100nC
0.4
0.2 20nC
0.00.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VBOOT_CAP (V)
FIGURE 5. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the switching
frequency and total gate charge of the selected MOSFETs.
Calculating the power dissipation in the driver for a desired
application is critical to ensuring safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of 125°C. The maximum allowable IC power
FN9132 Rev.2.00
Mar 23, 2007
dissipation for the SO-8 package is approximately 800mW.
When designing the driver into an application, it is
recommended that the following calculation be performed to
ensure safe operation at the desired frequency for the selected
MOSFETs. The power dissipated by the driver is approximated
as:
P = fsw1.5VUQU + VLQL + IVCCVCC
where fsw is the switching frequency of the PWM signal. VU
and VL represent the upper and lower gate rail voltage. QU and
QL is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to the
gate pins. The IVCC VCC product is the quiescent power of the
driver and is typically negligible.
1000
900
QU =100nC
800 QL = 200nC
700
QU =50nC
QL = 100nC
QU = 50nC
QL = 50nC
600
QU = 20nC
500
QL = 50nC
400
300
200
100
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
FIGURE 6. POWER DISSIPATION vs FREQUENCY
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and power devices (both
upper and lower FETs) could cause increased PHASE ringing,
which may lead to voltages that exceed the absolute maximum
rating of the devices. When PHASE rings below ground, the
negative voltage could add charge to the bootstrap capacitor
through the internal bootstrap diode. Under worst-case
conditions, the added charge could overstress the BOOT
and/or PHASE pins. To prevent this from happening, the user
should perform a careful layout inspection to reduce trace
inductances, and select low lead inductance MOSFETs and
drivers. D2PAK and DPAK packaged MOSFETs have high
parasitic lead inductances, as opposed to SOIC-8. If higher
inductance MOSFETs must be used, a Schottky diode is
recommended across the lower MOSFET to clamp negative
PHASE ring.
A good layout would help reduce the ringing on the phase and
gatenodes significantly:
Page 7 of 10
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