MC33991DW View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MC33991DW

Gauge Driver Integrated Circuit

Freescale Semiconductor 

TIMING DESCRIPTIONS AND DIAGRAMS

COMMUNICATION MEMORY MAPS

TIMING DESCRIPTIONS AND DIAGRAMS

CSC S B

In te rn a l re g is te rs a re

lo a d e d s om e tim e

afte r th is e d g e

SCLK

SCLK

SI S I

D15 D14

D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SOS O

OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

O u tp u t s h ift re g is te r is

loa de d h ere

N O T E S : 1 . S O is tr i-s taCtSe diswlohgeicn1C. S B is lo g ic 1 .

Figure 5. Single 16-Bit Word SPI Communication

CSC S B

SCLK

SCLK

SI S I

D15 D14

D13

SO S O

OD15 OD14 OD13

D2

D1

D0 D15* D14* D13*

OD2 OD1 OD0 D15 D14 D13

D2*

D1* D0*

D2

D1

D0

NOTES: 1.

2.

3.

4.

S O is tri- s ta te d w h e n CCSSiBs loisgilco 1g.ic 1 .

D 1 5 , D 1 4 , D 1 3 , ..., a n d D 0 re fe r to th e fir s t 1 6 b its o f d a ta in to th e 3G39D9I1C. .

D 1 5 * , D 1 4 * , D 1 3 * , ... , a n d D 0 * re fe r to th e m o s t re c e n t e n try o f p ro g r a m d a ta in to th e 3G3D99I1C..

O D 1 5 , O D 1 4 , O D 1 3 , ..., a n d O D 0 r e fe r to th e firs t 1 6 b its o f fa u lt a n d s ta tu s d a ta o u t o f th e 3G39D9I1C. .

Figure 6. Multiple 16-Bit Word SPI Communication

DATA INPUT

The input Shift register captures data at the falling edge of

the SCLK clock. The SCLK clock pulses exactly 16 times only

inside the transmission windows (CS in a logic [0] state). By

the time the CS signal goes to logic [1] again, the contents of

the Input Shift register are transferred to the appropriate

internal register, according to the address contained in bits

15-13. The minimum time CS should be kept high depends

on the internal clock speed. That data is specified in the SPI

Interface Timing Table. It must be long enough so the internal

clock is able to capture the data from the input Shift register

and transfer it to the internal registers.

DATA OUTPUT

At the first rising edge of the SCLK clock, with the CS at

logic [0], the contents of the Status Word register are

transferred to the Output Shift register. The first 16 bits

clocked out are the status bits. If data continues to clock in

before the CS transitions to a logic [1], the device to shift out

the data previously clocked in FIFO after the CS first

transitioned to logic [0].

COMMUNICATION MEMORY MAPS

The 33991device is capable of interfacing directly with a

micro controller, via the 16-bit SPI protocol described and

specified below. The device is controlled by the

microprocessor and reports back status information via the

SPI. This section provides a detailed description of all

registers accessible via serial interface. The various registers

control the behavior of this device.

A message is transmitted by the master beginning with the

MSB (D15) and ending with the LSB (D0). Multiple

messages can be transmitted in succession to accommodate

those applications where daisy chaining is desirable, or to

confirm transmitted data, as long as the messages are all

multiples of 16 bits. Data is transferred through daisy chained

devices, illustrated in Figure 5. If an attempt is made to latch

in a message smaller than 16 bits wide, it is ignored.

The 33991 uses six registers to configure the device and

control the state of the four H-bridge outputs. The registers

are addressed via D15-D13 of the incoming SPI word, in

Table 2.

Analog Integrated Circuit Device Data

Freescale Semiconductor

33991

13

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