ISL90842 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
ISL90842
Renesas Electronics
ISL90842 Datasheet PDF : 10 Pages
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ISL90842
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 1) MAX
tDCP
DCP wiper response time
SCL falling edge of last bit of DCP data byte
1
(Note 8)
to wiper change
SERIAL INTERFACE SPECS
VIL
A1, A0, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*VCC
VIH
A1, A0, SDA, and SCL input buffer
HIGH voltage
0.7*VCC
VCC+0.3
Hysteresis SDA and SCL input buffer hysteresis
(Note 8)
VOL
SDA output buffer LOW voltage,
(Note 8) sinking 4mA
0.05*
VCC
0
0.4
Cpin
A1, A0, SDA, and SCL pin
10
(Note 8) capacitance
fSCL
SCL frequency
400
tIN
Pulse width suppression time at SDA Any pulse narrower than the max spec is
50
(Note 8) and SCL inputs
suppressed
tAA
SCL falling edge to SDA output data SCL falling edge crossing 30% of VCC, until
900
(Note 8) valid
SDA exits the 30% to 70% of VCC window
tBUF
(Note 8)
Time the bus must be free before the SDA crossing 70% of VCC during a STOP
start of a new transmission
condition, to SDA crossing 70% of VCC
during the following START condition
1300
tLOW
tHIGH
tSU:STA
Clock LOW time
Clock HIGH time
START condition setup time
tHD:STA START condition hold time
tSU:DAT Input data setup time
tHD:DAT Input data hold time
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
1300
600
600
600
100
0
tSU:STO STOP condition hold time
From SCL rising edge crossing 70% of VCC, 600
to SDA rising edge crossing 30% of VCC
tHD:STO STOP condition hold time for read, or From SDA rising edge to SCL falling edge.
600
volatile only write
Both crossing 70% of VCC
tDH
Output data hold time
(Note 8)
From SCL falling edge crossing 30% of VCC,
0
until SDA enters the 30% to 70% of VCC
window
tR
SDA and SCL rise time
(Note 8)
From 30% to 70% of VCC
20 +
250
0.1 * Cb
tF
SDA and SCL fall time
(Note 8)
From 70% to 30% of VCC
20 +
250
0.1 * Cb
Cb (Note 8) Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
Rpu
SDA and SCL bus pull-up resistor off- Maximum is determined by tR and tF
1
(Note 8) chip
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
UNIT
µs
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
k
FN8096 Rev 1.00
January 16, 2006
Page 4 of 10
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