AD5100YRQZ-0 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD5100YRQZ-0

System Management IC with Factory Programmed Quad Voltage Monitoring and Supervisory Functions

Analog Devices 

AD5100

Parameter

MR Pull-Up Resistance (Internal to V3MON)

RESET Hold Time Tolerance

(see Figure 12 and Table 8)

SERIAL INTERFACES

Input Logic High (SCL, SDA)6

Input Logic Low (SCL, SDA)

Output Logic High (SDA)

Output Logic Low (SDA)

Input Current

Input Capacitance

POWER SUPPLY

Supply Voltage Range

Sleep Mode Supply Current

Active Mode Supply Current

Device Power-On Threshold

Device Power-Up V2MON, Minimum Pulse Width

Device Power-Down Delay

Symbol

ΔtRS_HOLD

Conditions

Min

37

TA = 25°C; does not apply to Code −10

0x6 and Code 0x7

TA = −40°C to +125°C; does not

−17

apply to Code 0x06 and Code 0x7

Typ1 Max

60

82

+10

+17

VIH

External RPULL-UP = 2.2 kΩ

VIL

External RPULL-UP = 2.2 kΩ

VOH

VRAIL = 2 V to 5.5 V

VOL

IOL = 3 mA

VIN = 0 V to 5.5 V

CI

2.0

5.5

0

0.8

0.7 × VRAIL

0

0.4

1

5

V1MON

6.0

ISLEEP_V1MON

V2MON = 0 V

IPOWER_V1MON

V2MON = 12 V

V2MON edge triggered mode selected

V2MON, IH

2.2

V2MON, IL

tV2MON_PW

4

TVREG_OFF_DELAY V2MON < 0.4 V (normal mode)

I2C-initiated power-down

30

5

2

2

0.4

2

10

Unit

kΩ

%

%

V

V

V

V

μA

pF

V

μA

mA

mA

V

V

ms

sec

μs

1 Represent typical values at 25°C, V1MON = 12 V, and V2MON = 12 V.

2 Initial V2MON turn-on minimum remains as 2.2 V but the 3 V to 30 V specifications apply afterward.

3 Does not apply if V2MON is a digital signal.

4 V4MON threshold limits (see Table 6) are designed to primarily allow V4MON to monitor low voltage inputs. The V4MON input pin is capable of withstanding voltages up to

30 V. One application where this 30 V capability is useful is electronic media-oriented systems transport (eMOST) diagnostic circuits.

5 The RESET short-circuit current is the maximum pull-up current when RESET is driven low by a microprocessor bidirectional reset pin.

6 It is typical for the SCL and SDA to have resistors pulled up to V3MON. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are

driven directly from a low voltage logic controller without pull-up resistors.

Rev. A | Page 6 of 36

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