AD5273BRJZ1-R2 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5273BRJZ1-R2 Datasheet PDF : 20 Pages
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Data Sheet
AD5273
Parameter
DYNAMIC CHARACTERISTICS7, 13, 14
Bandwidth, −3 dB
Total Harmonic Distortion
Adjustment Settling Time
Power-Up Settling Time—
After Fuses Blown
Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS7, 14, 15
SCL Clock Frequency
tBUF Bus Free Time Between
Stop and Start
tHD; STA Hold Time
(Repeated Start)
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU; STA Setup Time for
Start Condition
tHD; DAT Data Hold Time
tSU; DAT Data Setup Time
tF Fall Time of Both SDA and
SCL Signals
tR Rise Time of Both SDA and
SCL Signals
tSU; STO Setup Time for Stop Condition
OTP Program Time
Symbol
BW_1 kΩ
BW_10 kΩ
BW_50 kΩ
BW_100 kΩ
THDW
tS1
tS2
eN_WB
fSCL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Test Conditions/Comments
Min
RAB = 1 kΩ, code = 0x20
RAB = 10 kΩ, code = 0x20
RAB = 50 kΩ, code = 0x20
RAB = 100 kΩ, code = 0x20
VA = 1 V rms, RAB = 1 kΩ, VB = 0 V,
f = 1 kHz
VA = 5 V ± 1 LSB error band,
VB = 0 V, measured at VW
VA = 5 V ± 1 LSB error band,
VB = 0 V, measured at VW, VDD = 5 V
RAB = 1 kΩ, f = 1 kHz, code = 0x20
Applies to all parts
1.3
After this period, the first clock 0.6
pulse is generated
1.3
0.6
0.6
0.1
0.6
Typ1
Max
6000
600
110
60
0.05
5
5
3
400
50
0.9
0.3
0.3
400
Unit
kHz
kHz
kHz
kHz
%
µs
µs
nV/√Hz
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ms
1 Typical values represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 ∆RWB/∆T = ∆RWA/∆T. Temperature coefficient is code-dependent; see the Typical Performance Characteristics section.
5 INL and DNL are measured at VW. INL with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VW with the RDAC configured as a
potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating
conditions.
6 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
7 Guaranteed by design; not subject to production test.
8 The minimum voltage requirement on the VIH is 0.7 × VDD. For example, VIH min = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.
However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
9 Different from the operating power supply; the power supply for OTP is used one time only.
10 Different from the operating current; the supply current for OTP lasts approximately 400 ms for the one time it is needed.
11 See Figure 28 for the energy plot during the OTP program.
12 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13 Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.
The highest R value results in the minimum overall power consumption.
14 All dynamic characteristics use VDD = 5 V.
15 See Figure 29 for the location of the measured values.
Rev. J | Page 5 of 20
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