ATMEGA161-4JI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATMEGA161-4JI Datasheet PDF : 134 Pages
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Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock
cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing – enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
Figure 4. The ATmega161 AVR RISC Architecture
AVR ATmega161 Architecture
Data Bus 8-bit
8K x 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registers
ALU
1024 x 8
Data
SRAM
512 x 8
EEPROM
32
I/O Lines
Interrupt
Unit
SPI
Unit
Serial
UART0
Serial
UART1
8-bit
Timer/Counter
with PWM
and RTC
16-bit
Timer/Counter
with PWM
8-bit
Timer/Counter
with PWM
Watchdog
Timer
Analog
Comparator
6
ATmega161(L)
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