ATMEGA161 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATMEGA161 Datasheet PDF : 134 Pages
| |||
ATmega161(L)
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 4 shows the ATmega161 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing
them to be accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, and
other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the regis-
ter file, $20 - $5F.
The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The program
memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is
Self-programmable Flash memory.
With the jump and call instructions, the whole 8K word address space is directly accessed. Most AVR instructions have a
single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effec-
tively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the
usage of the SRAM. All user programs must initialize the SP (Stack Pointer) in the reset routine (before subroutines or
interrupts are executed). The 16-bit stack pointer is read/write accessible in the I/O space.
The 1K bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
7
Share Link: 