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ADN2847ACP-32 View Datasheet(PDF) - Analog Devices

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ADN2847ACP-32 Datasheet PDF : 12 Pages
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ADN2847
Caution must be taken when choosing component values for
ac coupling to ensure that the time constants (L/R and RC, see
Figure 12) are sufficiently long for the data rate and expected
number of CIDs (consecutive identical digits). Failure to do this
could lead to pattern dependent jitter and vertical eye closure.
For designs with low series resistance, or where external components
become impractical, the ADN2847 supports direct connection
to the laser diode (see Figure 11). In this case, care must be
taken to ensure that the voltage drop across the laser diode does
not violate the minimum compliance voltage on the IMODP pin.
Optical Supervisor
The PSET and ERSET potentiometers may be replaced with a
dual-digital potentiometer, the ADN2850 (see Figure 10). The
ADN2850 provides an accurate digital control for the average
optical power and extinction ratio and ensures excellent stability
over temperature.
VCC
VCC
IMPD
VCC
ADN2847
ADN2850
IMODP
TX SDI
RX SDO
DAC1
PSET
IBIAS
CLK
CS
CLK
CS
DAC2
ERSET
DATAP
DATAN
IDTONE
Figure 10. Application Using the ADN2850 a Dual 10-Bit
Digital Potentiometer with an Extremely Low Temperature
Coefficient as an Optical Supervisor
ALS
1k
VCC
1.5k
1.5k
36
25
FAIL
DEGRADE
37
GND2
VCC
VCC *
VCC2
IMODN
MPD
LD
*
*
*
IMODN
GND2
IMODP
IMODP
GND2
GND2
10H
48
VCC
IBIAS
IBIAS
CCBIAS
1
LD = LASER DIODE
MPD = MONITOR PHOTODIODE
ADN2847
GND 24
GND
GND
CLKN
CLKP
10nF
10nF
CLKN
CLKP
GND1
DATAP
DATAN
10nF
10nF
DATAP
DATAN
GND1
VCC1
GND
PAVCAP
ERCAP
22nF
22nF
13
** **
1.5k
12
VCCs SHOULD HAVE BYPASS CAPACITORS AS
CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS
ON THE ADN2847 AND THE LASER DIODE USED.
CONSERVATIVE DECOUPLING WOULD INCLUDE
100pF CAPACITORS IN PARALLEL WITH 10nF
CAPACITORS.
VCC
100nF 100nF 100nF 100nF 10F
NOTES
GND
* DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED.
** FOR DIGITAL PROGRAMMING,THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED.
Figure 11. DC-Coupled 3.3 Gbps Test Circuit, Data Not Clocked
REV. 0
–9–

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