D2-45057 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
D2-45057 Datasheet PDF : 30 Pages
| |||
D2-45057, D2-45157
Performance Specifications TA = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%.
All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
rDS(ON) (Maximum, MOSFETs at +25°C)
rDS(ON) Mismatch
PWM Switching Rate
rDS(ON)
-
200
-
mΩ
-
1
-
%
-
384
-
kHz
nPDN Input Off Delay
nPDN Input On Delay
POWER OUTPUT
tPDNOFF
-
1.4
-
ms
tPDNON
-
1.4
-
ms
<1% THD, Bridged, Load = 8Ω, HVDD[A:D] = 24V
<10% THD, Bridged, Load = 8Ω, HVDD[A:D] = 24V
<1% THD, Half-Bridge, Load = 8Ω, HVDD[A:D] = 24V
<10% THD, Half-Bridge, Load = 8Ω, HVDD[A:D] = 24V
THD+N
POUT
-
25
-
W
POUT
-
30
-
W
POUT
-
7
-
W
POUT
-
9
-
W
Load = 8Ω, Power = 25W, Bridged, 1kHz
THD+N
-
0.3
-
%
Load = 8Ω, Power = 1W, Bridged, 1kHz
-
0.05
-
%
SNR
SNR
-
110
-
dB
Efficiency (Power Stage, Load = 8Ω)
-
90
-
%
Serial Audio Interface Port Timing TA = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%.
All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tcSCLK
twSCLK
tsLRCLK
thLRCLK
tsSDI
thSDI
SCLK Frequency - (SCLK)
SCLK Pulse Width (high and low) - (SCLK)
LRCKR Set-Up to SCLK Rising - (LRCK)
LRCKR Hold from SCLK Rising - (LRCK)
SDIN Set-Up to SCLK Rising - (SDIN)
SDIN Hold from SCLK Rising - (SDIN)
-
-
12.5
MHz
40
-
-
ns
20
-
-
ns
20
-
-
ns
20
-
-
ns
20
-
-
ns
SCLK
tcSCLK
thLRCLK
LRCK
SDIN
tsLRCLK
twSCLK
twSCLK
tsSDI
thSDI
FIGURE 2. SERIAL AUDIO INTERFACE PORT TIMING
FN6785 Rev 1.00
May 5, 2016
Page 6 of 30
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