D2-45057 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
D2-45057 Datasheet PDF : 30 Pages
| |||
D2-45057, D2-45157
Two-Wire (I2C) Interface Port Timing TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at
0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
fSCL
SCL Frequency
tbuf
Bus Free Time Between Transmissions
twlowSCLx
SCL Clock Low
twhighSCLx
SCL Clock High
tsSTA
Set-Up Time For a (Repeated) Start
thSTA
Start Condition Hold Time
thSDAx
SDA Hold From SCL Falling (Note 11)
tsSDAx
SDA Set-Up Time to SCL Rising
tdSDAx
SDA Output Delay Time From SCL Falling
tr
Rise Time of Both SDA and SCL (Note 12)
tf
Fall Time of Both SDA and SCL (Note 12)
tsSTO
Set-Up Time For a Stop Condition
NOTES:
11. Data is clocked in as valid on next XTALI rising edge after SCL goes low.
12. Limits established by characterization and not production tested.
-
100
4.7
-
4.7
-
4.0
-
4.7
-
4.0
-
1 (typical)
250
-
-
3.5
-
1
-
300
4.7
-
kHz
µs
µs
µs
µs
µs
sys clk
ns
µs
µs
ns
µs
twhighSCLx
twlowSCLx
SCLx
tr
tf
tsSTA
SDAx
(INPUT)
SDAx
(OUTPUT)
thSDAx
tsSTO
tsSDAx
tbuf
thSTAx
tdSDAx
FIGURE 3. I2C INTERFACE TIMING
FN6785 Rev 1.00
May 5, 2016
Page 7 of 30
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