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D2-45057 View Datasheet(PDF) - Renesas Electronics

Part Name
Description
Manufacturer
D2-45057 Datasheet PDF : 30 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
D2-45057, D2-45157
SPI™ Master Mode Interface Port Timing TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds
at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
tV
MOSI Valid From Clock Edge
tS
MISO Setup to Clock Edge
tH
MISO Hold From Clock Edge
tWI
nSS Minimum Width
-
8
ns
10
-
ns
1 system clock + 2ns
3 system clocks + 2ns
SPI™ Slave Mode Interface Port Timing TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at
0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
tV
MISO Valid From Clock Edge
tS
MOSI Set-Up to Clock Edge
tH
MOSI Hold From Clock Edge
tWI
nSS Minimum Width
3 system clocks + 2ns
10
-
ns
1 system clock + 2ns
3 system clocks + 2ns
SCK(CPHA = 1, CPOL = 0)
SCK(CPHA = 0, CPOL = 0)
MOSI
MISO(CPHA = 0)
tV
tV
tH
tS
tWI
nSS
FIGURE 4. SPI TIMING
FN6785 Rev 1.00
May 5, 2016
Page 8 of 30

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