ADSP-21160NCBZ-100(RevD) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-21160NCBZ-100 Datasheet PDF : 58 Pages
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ADSP-21160M/ADSP-21160N
Table 3. Pin Function Descriptions (Continued)
Pin
CLKOUT
RESET
TCK
TMS
TDI
TDO
TRST
EMU
CIF
VDDINT
VDDEXT
AVDD
AGND
GND
NC
Type
O/T
I/A
I
I/S
I/S
O
I/A
O (O/D)
O/T
P
P
P
G
G
Function
Local Clock Out. CLKOUT is driven at the CLKIN frequency by the processor. This output can be
three-stated by setting the COD bit in the SYSCON register. A keeper latch on the DSP’s CLKOUT
pin maintains the output at the level it was last driven (only enabled on the processor with
ID2-0 = 00x). Do not use CLKOUT in multiprocessing systems; use CLKIN instead.
Processor Reset. Resets the ADSP-21160x to a known state and begins execution at the program
memory location specified by the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
Test Clock (JTAG). Provides a clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k internal pull-up
resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k internal
pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-
up or held low for proper operation of the ADSP-21160x. TRST has a 20 k internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21160x emulator target board connector only.
EMU has a 50 k internal pull-up resistor.
Core Instruction Fetch. Signal is active low when an external instruction fetch is performed. Driven
by bus master only. Three-state when host is bus master. CIF has a 20 k internal pull-up resistor
that is enabled on the ADSP-21160x with ID2–0 = 00x.
Core Power Supply. Nominally 2.5 V (ADSP-21160M) or 1.9 V (ADSP-21160N) dc and supplies the
DSP’s core processor
I/O Power Supply. Nominally 3.3 V dc.
Analog Power Supply. Nominally 2.5 V (ADSP-21160M) or 1.9 V (ADSP-21160N) dc and supplies the
DSP’s internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added
filtering circuitry is required. For more information, see Power Supplies on page 9.
Analog Power Supply Return.
Power Supply Return.
Do Not Connect. Reserved pins that must be left open and unconnected.
Table 4. Boot Mode Selection
EBOOT
1
0
0
0
0
1
LBOOT
0
0
1
0
1
1
BMS
Output
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
Booting Mode
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
Rev. D | Page 14 of 58 | September 2015
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