ADSP-21160NCBZ-100(RevD) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-21160NCBZ-100 Datasheet PDF : 58 Pages
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ADSP-21160M/ADSP-21160N
Single-instruction, multiple-data (SIMD)
architecture provides
Two computational processing elements
Concurrent execution—each processing element executes
the same instruction, but operates on different data
Code compatibility—at assembly level, uses the same
instruction set as the ADSP-2106x SHARC DSPs
Parallelism in buses and computational units allows
Single-cycle execution (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
Transfers between memory and core at up to four
32-bit floating- or fixed-point words per cycle
Accelerated FFT butterfly computation through a multiply
with add and subtract
Memory attributes
4M bits on-chip dual-ported SRAM for independent access
by core processor, host, and DMA
4G word address range for off-chip memory
Memory interface supports programmable wait state gen-
eration and page-mode for off-chip memory
DMA controller supports
14 zero-overhead DMA channels for transfers between
ADSP-21160x internal memory and external memory,
external peripherals, host processor, serial ports, or link
ports
64-bit background DMA transfers at core clock speed, in
parallel with full-speed processor execution
Host processor interface to 16- and 32-bit microprocessors
Multiprocessing support provides
Glueless connection for scalable DSP multiprocessing
architecture
Distributed on-chip bus arbitration for parallel bus con-
nect of up to 6 ADSP-21160x processors plus host
6 link ports for point-to-point connectivity and array
multiprocessing
Serial ports provide
Two synchronous serial ports with companding hardware
Independent transmit and receive functions
TDM support for T1 and E1 interfaces
64-bit-wide synchronous external port provides
Glueless connection to asynchronous and SBSRAM exter-
nal memories
Rev. D | Page 2 of 58 | September 2015
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