AN2061 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

AN2061

EEPROM Emulation with ST10F2xx

STMicroelectronics 

AN2061

the erase process (ex: reset) should be considered when designing the Flash management

software. This means that to design a robust Flash management software it is necessary to

have a deep understanding of the Flash erase process.

The Flash erase process is split in 3 phases:

– phase1: write all bits to 0, starting from the initial content. Interrupt during this phase will re-

sult in more memory cells with a “0” logic level; the content after interrupt in phase1 depends

on the Flash initial content.

– phase2: write all bits to 1, starting from the all “0” configuration. The longer the time before

this phase is interrupted, the higher number of cells will return a “1” logic level. The content

after interrupt in this phase does not depend on the Flash initial content; the content after

phase2 interrupt, shall be regarded as a totally random content.

– phase3: equalization. This phase is necessary to recover over-erased cells. The Flash man-

agement software for EEPROM emulation should guarantee that this phase was success-

fully completed before programming in this bank.

The consequence of interrupt during phase2 is that a single bit approach should be avoided

to flag the completion of the erasing process (see more details in Section 3.5 ‘Data-set status

bits’ on page 7).

The consequence of interrupt during phase1 and/or phase2 is that it is recommended to have

fixed data inside the emulated EEPROM so that checksum can be run to tell which Flash bank

keeps the valid data.

The most important point is to ensure that the Flash has been completely erased (phase3 was

not interrupted) before programming data inside a bank.

Note: the design of Flash software management is easier if programming in a new bank is al-

ways made just after erasing of this bank (when erasing of one bank is necessary).

2.4 Additional information on Flash

Incremental programming: the Flash controller will accept to program a word that is already

programmed if the new word is adding more “0” bits.

Programming completion: programming completion is important to guarantee data retention

time; the programming is complete when the Flash controller status indicates the end of pro-

gramming without showing any error flag. If programming is interrupted (ex: supply fail, CPU

reset), the cells of the word being programmed will be partially programmed. This can result in

unstable “0”s when reading this word.

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