LTC1326 View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LTC1326 Datasheet PDF : 16 Pages
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LTC1326/LTC1326-2.5
TYPICAL PERFOR A CE CHARACTERISTICS
Reset Pulse Width
vs Temperature
225
220
215
210
205
200
195
190
– 60 – 40 – 20 0 20 40 60 80 100
TEMPERATURE (°C)
1326/2.5 G13
“Soft” Reset Pulse Width
vs Temperature
112.5
110.0
107.5
105.0
102.5
100.0
97.5
95.0
– 60 – 40 – 20 0 20 40 60 80 100
TEMPERATURE (°C)
1326/2.5 G14
PBR Assertion Time to Reset
vs Temperature
2.25
2.20
2.15
2.10
2.05
2.00
1.95
1.90
– 60 – 40 – 20 0 20 40 60 80 100
TEMPERATURE (°C)
1326/2.5 G15
PIN FUNCTIONS
VCC3 (Pin 1): 3.3V Sense Input and Power Supply Pin for
the IC. Bypass to ground with ≥ 0.1µF ceramic capacitor.
VCC5 (Pin 2) (LTC1326): 5V Sense Input. Used as gate
drive for the RST output FET when the voltage on VCC3 is
less than the voltage on VCC5. If unused, it can be tied to
VCC3 (see Dual and Single Supply Monitor Operation in
the Applications Information section).
VCC25 (Pin 2) (LTC1326-2.5): 2.5V Sense Input. Used as
gate drive for RST output FET when the voltage on VCC3
is less than the voltage on VCC25. If unused, it can be tied
to VCC3.
VCCA (Pin 3): 1V Sense, High Impedance Input. Can be
used as a logic input with a 1V threshold. If unused, it can
be tied to either VCC3 or VCC25.
GND (Pin 4): Ground.
RST (Pin 5): Reset Logic Output. Active high CMOS logic
output, drives high to VCC3, buffered complement of RST.
An external pull-down on the RST pin will drive this pin
high.
RST (Pin 6): Reset Logic Output. Active low, open-drain
logic output with weak pull-up to VCC3. Can be pulled up
greater than VCC3 when interfacing to 5V logic. Asserted
when one or more of the supplies are below trip
thresholds and held for 200ms after all supplies become
valid. Also asserted after PBR is held low for more than
2 seconds and for an additional 200ms after PBR is
released.
SRST (Pin 7): Soft Reset. Active low, open-drain logic
output with weak pull-up to VCC3. Can be pulled up
greater than VCC3 when interfacing to 5V logic. Asserted
for 100µs after PBR is held low for less than 2 seconds
and released.
PBR (Pin 8): Push-Button Reset. Active low logic input
with weak pull-up to VCC3. Can be pulled up greater than
VCC3 when interfacing to 5V logic. When asserted for less
than 2 seconds, outputs a soft reset 100µs pulse on the
SRST pin. When PBR is asserted for greater than 2
seconds, the RST output is forced low and remains low
until 200ms after PBR is released.
132625fc
6
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