DSP56852UM/D View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56852UM/D

16-bit Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

External Memory InterfaceTiming

4.6 External Memory InterfaceTiming

The External Memory Interface is designed to access static memory and peripheral devices. Figure 12

shows sample timing and parameters that are detailed in Table 10.

The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as

user controlled wait states. The equation:

t = D + P * (M + W)

should be used to determine the actual time of each parameter. The terms in the above equation are

defined as:

t parameter delay time

D fixed portion of the delay, due to on-chip path delays.

P the period of the system clock, which determines the execution rate of the part (i.e. when the

device is operating at 120 MHz, P = 8.33 ns).

M Fixed portion of a clock period inherent in the design. This number is adjusted to account for

possible clock duty cycle derating.

W the sum of the applicable wait state controls. See the “Wait State Controls” column of

Table 10 for the applicable controls for each parameter. See the EMI chapter of the 83x

Peripheral Manual for details of what each wait state field controls.

Some of the parameters contain two sets of numbers. These parameters have two different paths and clock

edges that must be considered. Check both sets of numbers and use the smaller result. The appropriate

entry may change if the operating frequency of the part changes.

The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters

contain two sets of numbers to account for this difference. The “Wait States Configuration” column of

Table 10 should be used to make the appropriate selection.

A0-Axx,CS

RD

WR

tAWR

tWRWR

tWR

tARDA

tRD

tARDD

tWAC

tWRRD

tRDA

tRDRD

tRDWR

D0-D15

tDWR

tDOS

Data Out

tDOH

tRDD

tAD

tDRD

Data In

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

Figure 12. External Memory Interface Timing

DSP56852 Technical Data

21

Preliminary

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