MPC8309VMAHFCA View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
MPC8309VMAHFCA
Freescale Semiconductor
MPC8309VMAHFCA Datasheet PDF : 81 Pages
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Overview
1 Overview
The MPC8309 incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology,
which includes 16 KB of each L1 instruction and data caches, dual integer units, and on-chip memory
management units (MMUs). The MPC8309 also includes a 32-bit PCI controller, two DMA engines and
a 16/32-bit DDR2 memory controller with 8-bit ECC.
A new communications complex based on QUICC Engine technology forms the heart of the networking
capability of the MPC8309. The QUICC Engine block contains several peripheral controllers and a 32-bit
RISC controller. Protocol support is provided by the main workhorses of the device—the unified
communication controllers (UCCs). A block diagram of the MPC8309 is shown in the following figure.
2x DUART
I2C
Timers
GPIO
SPI
RTC
Interrupt
Controller
e300c3 Core with Power
Management
16-KB
I-Cache
16-KB
D-Cache
FPU
ULPI
USB 2.0 HS
Host/Device/OTG
Enhanced
Local Bus
DDR2
Controller
QUICC Engine™ Block
Baud Rate
Generators
16 KB Multi-User RAM
Accelerators
48 KB Instruction RAM
Single 32-bit RISC CP Serial DMA
IO
4 FlexCAN Sequencer
eSDHC
DMA
Engine 2
DMA
Engine 1
PCI Controller
Time Slot Assigner
Serial Interface
2x TDM Ports 2 RMII/MII
2x HDLC
1 RMII/MII
2x IEEE 1588
Figure 1. MPC8309 block diagram
Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII
Ethernet, HDLC and TDM.
In summary, the MPC8309 provides users with a highly integrated, fully programmable communications
processor. This helps to ensure that a low-cost system solution can be quickly developed and offers
flexibility to accommodate new standards and evolving system requirements.
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
2
Freescale Semiconductor
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