MPC8349VVAJF View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8349VVAJF

PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications

Freescale Semiconductor 

DDR SDRAM

6 DDR SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8349E.

NOTE

The information in this document is accurate for revision 1.1 silicon and

earlier. For information on revision 3.0 silicon and earlier versions see the

MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware

Specifications. See Section 23.1, “Part Numbers Fully Addressed by This

Document,” for silicon revision level determination.

6.1 DDR SDRAM DC Electrical Characteristics

Table 11 provides the recommended operating conditions for the DDR SDRAM component(s) of the

MPC8349E.

Table 11. DDR SDRAM DC Electrical Characteristics

Parameter/Condition

Symbol

Min

Max

Unit Notes

I/O supply voltage

GVDD

2.375

2.625

V

1

I/O reference voltage

MVREF

0.49 × GVDD

0.51 × GVDD

V

2

I/O termination voltage

VTT

MVREF – 0.04

MVREF + 0.04

V

3

Input high voltage

VIH

MVREF + 0.18

GVDD + 0.3

V

Input low voltage

VIL

–0.3

MVREF – 0.18

V

Output leakage current

IOZ

–10

10

μA

4

Output high current (VOUT = 1.95 V)

IOH

–15.2

—

mA

Output low current (VOUT = 0.35 V)

IOL

15.2

—

mA

MVREF input leakage current

IVREF

—

5

μA

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.

Table 12 provides the DDR capacitance.

Table 12. DDR SDRAM Capacitance

Parameter/Condition

Symbol

Min

Max

Unit Notes

Input/output capacitance: DQ, DQS

CIO

6

8

pF

1

Delta input/output capacitance: DQ, DQS

CDIO

—

0.5

pF

1

Note:

1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

15

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