DDR SDRAM
Figure 4 shows the DDR SDRAM output timing for address skew with respect to any MCK.
MCK[n]
MCK[n]
tMCK
tAOSKEWmax)
ADDR/CMD
CMD
NOOP
tAOSKEW(min)
ADDR/CMD
CMD
NOOP
Figure 4. Timing Diagram for tAOSKEW Measurement
Figure 5 provides the AC test load for the DDR bus.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 5. DDR AC Test Load
Table 15 shows the DDR SDRAM measurement conditions.
Table 15. DDR SDRAM Measurement Conditions
Symbol
VTH
VOUT
Notes:
1. Data input threshold measurement point.
2. Data output measurement point.
DDR
MVREF ± 0.31 V
0.5 × GVDD
Unit Notes
V
1
V
2
MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
18
Freescale Semiconductor