Overview
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— All channels accessible to local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
• DUART
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
• Serial peripheral interface (SPI) for master or slave
• General-purpose parallel I/O (GPIO)
— 64 parallel I/O pins multiplexed on various chip interfaces
• System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
• Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan
• Integrated PCI bus and SDRAM clock generation
MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
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Freescale Semiconductor