MPC8349E View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
MPC8349E Datasheet PDF : 88 Pages
| |||
Clocking
NOTE
Core VCO frequency = core frequency × VCO divider
VCO divider must be set properly so that the core VCO frequency is in the
range of 800–1800 MHz.
Table 57. e300 Core PLL Configuration
RCWL[COREPLL]
0–1
2–5
6
core_clk : csb_clk Ratio
VCO Divider1
nn
0000
n
PLL bypassed
(PLL off, csb_clk clocks core directly)
PLL bypassed
(PLL off, csb_clk clocks core directly)
00
0001
0
1:1
2
01
0001
0
1:1
4
10
0001
0
1:1
8
11
0001
0
1:1
8
00
0001
1
1.5:1
2
01
0001
1
1.5:1
4
10
0001
1
1.5:1
8
11
0001
1
1.5:1
8
00
0010
0
2:1
2
01
0010
0
2:1
4
10
0010
0
2:1
8
11
0010
0
2:1
8
00
0010
1
2.5:1
2
01
0010
1
2.5:1
4
10
0010
1
2.5:1
8
11
0010
1
2.5:1
8
00
0011
0
3:1
2
01
0011
0
3:1
4
10
0011
0
3:1
8
11
0011
0
3:1
8
1 Core VCO frequency = core frequency × VCO divider. The VCO divider must be set properly so that the core VCO frequency
is in the range of 800–1800 MHz.
19.3 Suggested PLL Configurations
Table 58 shows suggested PLL configurations for 33 and 66 MHz input clocks.
MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
71
Share Link: 