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MPC8349E View Datasheet(PDF) - Freescale Semiconductor

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Description
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MPC8349E Datasheet PDF : 88 Pages
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Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8349E for the 3.3-V
signals, respectively.
Overvoltage
Waveform
11 ns
(Min)
+7.1 V
7.1 V p-to-p
(Min)
4 ns
(Max)
0V
4 ns
(Max)
62.5 ns
+3.6 V
Undervoltage
Waveform
7.1 V p-to-p
(Min)
–3.5 V
Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling
2.1.3 Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Driver Type
Local bus interface utilities signals
PCI signals (not including PCI output clocks)
PCI output clocks (including PCI_SYNC_OUT)
DDR signal
TSEC/10/100 signals
DUART, system control, I2C, JTAG, USB
GPIO signals
Output Impedance
(Ω)
40
25
40
18
40
40
40
Supply
Voltage
OVDD = 3.3 V
GVDD = 2.5 V
LVDD = 2.5/3.3 V
OVDD = 3.3 V
OVDD = 3.3 V,
LVDD = 2.5/3.3 V
2.2 Power Sequencing
MPC8349E does not require the core supply voltage and I/O supply voltages to be applied in any particular
order. Note that during the power ramp up, before the power supplies are stable, there may be a period of
time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O
pins are three-stated. To minimize the time that I/O pins are actively driven, it is recommended to apply
core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up.
MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
9

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