LC895124 View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LC895124 Datasheet PDF : 8 Pages
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LC895124
Pin Functions
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin
Pin No.
Symbol
Type
Function
1
VSS0
P
2
VSS0
P
3
VSS0
P
4
VSS0
P
5
ZRAS0
O Buffer RAM RAS signal output pin 0 (Normally, pin 0 is used)
6
ZRAS1
O Buffer RAM RAS signal output pin 1
7
ZCAS0
O Buffer RAM CAS signal output pin 0 (Normally, pin 0 is used)
8
ZCAS1
O Buffer RAM CAS signal output pin 1
9
ZOE
O Buffer RAM output enable
10
ZUWE
O Buffer RAM upper write enable
11
ZLWE
O Buffer RAM lower write enable
12
VSS0
P
13
RA0
O
14
RA1
O
15
RA2
O Buffer RAM address signal outputs
16
RA3
O
17
RA4
O
18
VDD
P
19
VSS0
P
20
RA5
O
21
RA6
O
Buffer RAM address signal outputs
22
RA7
O
23
RA8
O
24
RA9 (IO15)
B
25
RA10 (IO14)
B Address outputs for the buffer RAM or data I/O pins
26
RA11 (IO13)
B The pin circuits include pull-up resistors.
27
RA12 (IO12)
B
28
VSS0
P
29
RA13 (IO11)
B
30
RA14 (IO10)
B Address outputs for the buffer RAM or data I/O pins
31
RA15 (IO9)
B The pin circuits include pull-up resistors.
32
RA16 (IO8)
B
33
IO7
B
34
IO6
B Buffer RAM data I/O. The pin circuit includes a pull-up resistor.
35
IO5
B
36
VSS0
P
37
VDD
P
38
IO4
B
39
IO3
B
40
IO2
B
Address outputs for the buffer RAM or data I/O pins
The pin circuits include pull-up resistors.
41
IO1
B
42
IO0
B
43
VSS0
P
44
XTALCK0
I Crystal oscillator input
45
XTAL0
O Crystal oscillator output
46
VDD
P
47
MCK
O Outputs the XTALCK0 frequency, or that frequency divided by 2.
48
TEST0
I
49
TEST1
I Test pins. These pins must be connected to VSS0.
50
TEST2
I
Note: 1. NC pins must be left open. Do not connect any signal to these pins.
2. Pin names that start with Z are negative-logic signals.
3. VSS0 is the logic system ground and VSS1 is the SCSI interface ground.
4. Applications that use DRAM must insert resistors in the CAS and RAS lines, connect capacitors between these lines and ground, and take any
other measures necessary to prevent undershoot in the DRAM related circuits.
5. Since these circuits include buffers that sink 48 mA, adequate noise prevention measures must be applied.
Continued on next page.
No. 5240-4/8
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