MCM64PC64SG66 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MCM64PC64SG66 Datasheet PDF : 16 Pages
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TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 0.3 V, TJ = 20 to + 110°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . Figure 3 Unless Otherwise Noted
TAG RAM READ CYCLE (See Note 1 and 5)
Parameter
Symbol
Read Cycle Time
tAVAV
Address Access Time
tAVQV
Output Hold from Address Change
tAXQX
NOTES:
1. CWE is high for read cycle.
2. All timings are referenced from the last valid address to the first address transition.
3. Transition is measured ±500 mV from steady–state voltage with load of Figure 3B.
4. This parameter is sampled and not 100% tested.
5. Device is continuously selected (CG = VIL).
– 15
Min
Max
15
—
—
15
4
—
Unit
Notes
ns
2
ns
ns
3, 4
Ax (ADDRESS)
Q (DATA OUT)
TAG RAM READ CYCLE (See Note 5)
tAVAV
tAXQX
PREVIOUS DATA VALID
tAVQV
DATA VALID
OUTPUT
AC TEST LOADS
Z0 = 50 Ω
50 Ω
VL = 1.5 V
OUTPUT
351 Ω
3.3 V
317 Ω
5 pF
Figure 3A
Figure 3B
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
MCM64PC32•MCM64PC64
12
MOTOROLA FAST SRAM
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