MCM64PC64 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MCM64PC64 Datasheet PDF : 16 Pages
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PIN DESCRIPTIONS
160–Lead Card Edge Pin Locations
20, 21, 22, 23, 24, 26, 28, 29,
101, 102, 103, 104, 106, 108, 109, 110
36, 116
11, 12, 13, 14, 92, 93, 94, 96
8
18
17
16
31, 32
30
9
89
91
114
38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51,
53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,
67, 69, 70, 71, 73, 74, 75, 77, 78, 79,
118, 120, 121, 122, 124, 125, 126, 127,
129, 130, 131, 133, 134, 135, 137, 138,
139, 141, 142, 143, 145, 146, 147, 149,
150, 151, 153, 154, 155, 157, 158, 159
2, 3, 4, 5, 82, 83, 84, 85
33, 34, 112, 113
7, 15, 25, 39, 52, 60, 68, 76
87, 95, 105, 119, 132, 140, 148, 156
1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72,
80, 81, 90, 99, 107, 115, 117, 123, 128,
136, 144, 152, 160
6, 86, 88, 97, 98
100, 111
Symbol
A3 – A18
CLK0,
CLK1
CWE0 –
CWE7
TWE
BWE
GWE
CCS
ECS1,
ECS2
ADSP
CADS
CADV
CG
BOSEL
DQ0 –
DQ63
TIO0 –
TIO7
PD0 –
PD3
VDD3
VDD5
VSS
NC
RSVD
Type
Input
Input
Input
Description
Address Inputs: These inputs are registered into data RAMs and must
meet setup and hold times. The tag RAM addresses are not registered.
Clock: This signal registers the address, data in, and all control signals
except CG.
Cache Data Byte Write Enable: Active low write signal for data RAMs.
Input
Input
Input
Input
Input
Tag Write Enable: Active low write signal for tag RAMs.
Byte Write Enable: To be used in future modules.
Global Write Enable: To be used in future modules.
Chip Select: Active low chip enable for data RAMs.
Expansion Chip Select
Input
Input
Input
Input
Input
I/O
Address Status Processor: Initiates READ, WRITE, or chip deselect
cycle (Exception–chip deselect does not occur when ADSP is asserted
and CCS is high.
Cache Address Status: Initiates READ, WRITE, or chip deselect cycle.
Cache Burst Advance: Increments address count in accordance with
interleaved count style.
Cache Output Enable: Active low asynchronous input.
Low–enables output buffers (DQ pins)
High–DQx pins are high impedance.
Burst Order Select: NC for interleaved burst counter. Tie to ground for
linear burst counter.
Synchronous Data I/O:
Drives data out of data RAMs during READ cycles.
Stores data to data RAMs during WRITE cycles.
I/O Tag RAM I/O:
Drives data out during tag compare cycles.
Stores data to tag RAM during tag WRITE cycles.
— Presence Detect: See Presence Detect Table
Supply Power Supply: 3.3 V + 10%, – 5%.
Supply Power Supply: 5.0 V ± 5%.
Supply Ground
— No Connection: There is no connection to the module.
— No Connection: Reserved for future use.
MOTOROLA FAST SRAM
MCM64PC32•MCM64PC64
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