NCV500(2015) View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
NCV500 Datasheet PDF : 18 Pages
| |||
NCP500, NCV500
The maximum dissipation the package can handle is
given by:
PD
+
TJ(max) *TA
RqJA
If TJ is not recommended to exceed 125°C, then the
NCP500 can dissipate up to 400 mW @ 25°C.
The power dissipated by the NCP500 can be calculated
from the following equation:
Ptot + ƪVin * Ignd (Iout)ƫ ) [Vin * Vout] * Iout
or
VinMAX
+
Ptot ) Vout * Iout
Ignd ) Iout
If a 150 mA output current is needed the ground current
is extracted from the data sheet curves: 200 mA @ 150 mA.
For a NCP500SN18T1 (1.8 V), the maximum input voltage
will then be 4.4 V, good for a 1 Cell Li−ion battery.
Hints
Please be sure the Vin and GND lines are sufficiently wide.
When the impedance of these lines is high, there is a chance
to pick up noise or cause the regulator to malfunction.
Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads as short
as possible.
Package Placement
DFN packages can be placed using standard pick and
place equipment with an accuracy of "0.05 mm.
Battery or
Unregulated
Voltage
+
C1
1
2
ON
3
OFF
Vout
5
+
C2
4
Figure 27. Typical Application Circuit
Component pick and place systems are composed of a vision
system that recognizes and positions the component and a
mechanical system which physically performs the pick and
place operation. Two commonly used types of vision
systems are: (1) a vision system that locates a package
silhouette and (2) a vision system that locates individual
bumps on the interconnect pattern. The latter type renders
more accurate place but tends to be more expensive and time
consuming. Both methods are acceptable since the parts
align due to a self−centering feature of the DFN solder joint
during solder re−flow.
Solder Paste
Type 3 or Type 4 solder paste is acceptable.
Re−flow and Cleaning
The DFN may be assembled using standard IR/IR
convection SMT re−flow processes without any special
considerations. As with other packages, the thermal profile
for specific board locations must be determined. Nitrogen
purge is recommended during solder for no−clean fluxes.
The DFN is qualified for up to three re−flow cycles at 235°C
peak (J−STD−020). The actual temperature of the DFN is a
function of:
• Component density
• Component location on the board
• Size of surrounding components
ON
OFF
1
2
Battery or
Unregulated
3
Voltage
+
C1
6
5
Vout
4
+
C2
Figure 28. Typical Application Circuit
www.onsemi.com
13
Share Link: 