HYB39S256160T-8B View Datasheet(PDF) - Siemens AG
Part Name
Description
Manufacturer
HYB39S256160T-8B Datasheet PDF : 56 Pages
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HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Column
Address Counter
Column Addresses
A0 - A9, AP,
BA0, BA1
Column
Address Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh
Counter
Row
Decoder
Memory
Array
Bank 0
8192 x
1024 x
8 Bit
Row
Decoder
Memory
Array
Bank 1
8192 x
1024 x
8 Bit
Row
Decoder
Memory
Array
Bank 2
8192 x
1024 x
8 Bit
Row
Decoder
Memory
Array
Bank 3
8192 x
1024 x
8 Bit
Input Buffer Output Buffer
DQ0 - DQ7
Control Logic & Timing Generator
*) on SSTL versions only
CLK CKE CS RAS CAS WE DQM VREF*)
SPB03780
Block Diagram for 32 M × 8 SDRAM (13/10/2 addressing)
Semiconductor Group
5
1998-10-01
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