IDT79R4640100DU View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT79R4640100DU

LOW-COST EMBEDDED ORION™ RISC MICROPROCESSOR

Integrated Device Technology 

R4640/RV4640

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE

Table 2 gives the latencies of some of the floating-point

instructions in internal processor cycles.

Operation

ADD

SUB

MUL

DIV

SQRT

CMP

Instruction

Latency

4

4

8

32

31

3

System Control Coprocessor Registers

The R4640 incorporates all system control co-

processor (CP0) registers on-chip. These registers

provide the path through which the virtual memory

system’s address translation is controlled, exceptions are

handled, and operating modes are controlled (kernel vs.

user mode, interrupts enabled or disabled, cache

features). In addition, the R4640 includes registers to

implement a real-time cycle counting facility, which aids in

cache diagnostic testing, assists in data error detection,

and facilitates software debug. Alternatively, this timer

can be used as the operating system reference timer, and

can signal a periodic interrupt.

Table 3 shows the CP0 registers of the R4640.

FIX

4

FLOAT

6

Number Name

0 IBase

Function

Instruction address space base (new in

R4640)

ABS

1

MOV

1

NEG

1

LWC1

2

1 IBound

Instruction address space bound (new

in R4640)

2 DBase

Data address space base (new in

R4640)

3 DBound Data address space bound (new in

R4640)

SWC1

1

Table 2: Floating-Point Operation

4-7, 10, -

20-25,

29, 31

Not used

Floating-Point General Register File

The floating-point register file is made up of thirty-two

32-bit registers. These registers are used as source or

target registers for the single-precision operations.

References to these registers as 64-bit registers (as

supported in the R4700) will cause a trap to be signalled

to the integer unit.

The floating-point control register space contains two

registers; one for determining configuration and revision

information for the coprocessor and one for control and

status information. These are primarily involved with

diagnostic software, exception handling, state saving and

restoring, and control of rounding modes.

8 BadVAddr Virtual address on address exceptions

9 Count

Counts every other cycle

11 Compare Generate interrupt when Count =

Compare

12 Status

Miscellaneous control/status

13 Cause

Exception/Interrupt information

14 EPC

Exception PC

15 PRId

Processor ID

16 Config

Cache and system attributes

17 CAlg

Cache attributes for the 8 512MB

regions of the virtual address space

System Control Coprocessor (CP0)

The system control coprocessor in the MIPS archi-

tecture is responsible for the virtual to physical address

translation and cache protocols, the exception control

system, and the diagnostics capability of the processor. In

the MIPS architecture, the system control coprocessor

(and thus the kernel software) is implementation

dependent.

In the R4640, significant changes in CP0 relative to the

R4600 have been implemented. These changes are

designed to simplify memory management, facilitate

debug, and speed real-time processing.

18 IWatch

Instruction breakpoint virtual address

19 DWatch Data breakpoint virtual address

26 ECC

Used in cache diagnostics

27 CacheErr Cache diagnostic information

28 TagLo

Cache index information

30 ErrorEPC CacheError exception PC

Table 3: R4640 CPO Registers

Operation modes

The R4640 supports two modes of operation: user

mode and kernel mode.

Kernel mode operation is typically used for exception

handling and operating system kernel functions, including

4

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