IDT79R465080MS View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT79R465080MS Datasheet PDF : 22 Pages
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IDT79R4650
COMMERCIAL TEMPERATURE RANGE
Boot Time Options
Fundamental operational modes for the processor are
initialized by the boot-time mode control interface. The
boot-time mode control interface is a serial interface
operating at a very low frequency (MasterClock divided by
256). The low-frequency operation allows the initialization
information to be kept in a low-cost EPROM; alternatively
the twenty-or-so bits could be generated by the system
interface ASIC or a simple PAL.
Immediately after the VCCOK Signal is asserted, the
processor reads a serial bit stream of 256 bits to initialize
all fundamental operational modes. After initialization is
complete, the processor continues to drive the serial clock
output, but no further initialization bits are read.
Boot-Time Modes
The boot-time serial mode stream is defined in Table 5.
Bit 0 is the bit presented to the processor when VCCOK is
asserted; bit 255 is the last.
Power Management
CP0 is also used to control the power management for
the R4650. This is the standby mode and it can be used to
reduce the power consumption of the internal core of the
CPU. The standby mode is entered by executing the WAIT
instruction with the SysAD bus idle and is exited by any
interrupt.
Once the CPU is in Standby Mode, any interrupt, including
the internally generated timer interrupt, will cause the CPU to
exit Standby Mode.
Mode bit
0
4..1
7..5
Description
Reserved (must be zero)
Writeback data rate:
64-bit
0→D
1 → DDx
2 → DDxx
3 → DxDx
4 → DDxxx
5 → DDxxxx
6 → DxxDxx
7 → DDxxxxxx
8 → DxxxDxxx
9-15 reserved
32-bit
0→W
1 → WWx
2 → WWxx
3 → WxWx
4 → WWxxx
5 → WWxxxx
6 → WxxWxx
7 → WWxxxxxx
8 → WxxxWxxx
9-15 reserved
Clock multiplier:
0→2
1→3
2→4
3→5
4→6
5→7
6→8
7 reserved
Standby Mode Operation
The R4650 provides a means to reduce the amount of
power consumed by the internal core when the CPU would
otherwise not be performing any useful operations. This is
known as “Standby Mode”.
8
10..9
0 → Little endian
1 → Big endian
00 → R4000 compatible
01 → reserved
10 → pipelined writes
11 → write re-issue
Entering Standby Mode
Executing the WAIT instruction enables interrupts and
enters Standby mode. When the WAIT instruction finishes
the W pipe-stage, if the SysAd bus is currently idle, the
internal clocks will shut down, thus freezing the pipeline.
The PLL, internal timer, and some of the input pins
(Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will
continue to run. If the conditions are not correct when the
WAIT instruction finishes the W pipe-stage (i.e. the SysAd
bus is not idle), the WAIT is treated as a NOP.
11
12
14..13
255..15
Disable the timer interrupt on Int[5]
0 → 64-bit system interface
1 → 32-bit system interface
Output driver strength:
10 → 100% strength (fastest)
11 → 83% strength
00 → 67% strength
01 → 50% strength (slowest)
Must be zero
Table 5: Boot time mode stream
5.8
10
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