IDT79R4650133MS(1996) View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT79R4650133MS Datasheet PDF : 22 Pages
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IDT79R4650
Write buffer
Writes to external memory, whether cache miss write-
backs or stores to uncached or write-through addresses,
use the on-chip write buffer. The write buffer holds up to
four address and data pairs. The entire buffer is used for a
data cache writeback and allows the processor to proceed
in parallel with memory update. For uncached and write-
through stores, the write buffer significantly increases
performance over the R4000 family of processors.
System Interface
The R4650 supports a 64-bit system interface that is bus
compatible with the R4600 system interface. In addition,
the R4650 supports a 32-bit system interface mode,
allowing the CPU to interface directly with a lower cost
memory system.
The interface consists of a 64-bit Address/Data bus with
8 check bits and a 9-bit command bus protected with parity.
In addition, there are 8 handshake signals and 6 interrupt
inputs. The interface has a simple timing specification and
is capable of transferring data between the processor and
memory at a peak rate of 533MB/sec at 133MHz.
Figure 4 shows a typical system using the R4650. In this
example two banks of DRAMs are used to supply and
accept data with a DDxxDD data pattern.
The R4650 clocking interface allows the CPU to be easily
mated with external reference clocks. The CPU input clock
is the bus reference clock, and can be between 25 and
67MHz (somewhat dependent on maximum pipeline speed
for the CPU).
An on-chip phase-locked-loop generates the pipeline
clock from the system interface clock by multiplying it up an
amount selected at system reset. Supported multipliers are
values 2 through 8 inclusive, allowing systems to
implement pipeline clocks at significantly higher frequency
than the system interface clock.
COMMERCIAL TEMPERATURE RANGE
System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to
transfer addresses and data between the R4650 and the
rest of the system. It is protected with an 8-bit parity check
bus, SysADC. When initialized for 32-bit operation, SysAD
can be viewed as a 32-bit multiplexed bus, with 4 parity
check bits.
The system interface is configurable to allow easier inter-
facing to memory and I/O systems of varying frequencies.
The bus frequency and reference timing of the R4650 are
taken from the input clock. The rate at which the CPU
transmits data to the system interface is programmable via
boot time mode control bits. The rate at which the
processor receives data is fully controlled by the external
device. Therefore, either a low cost interface requiring no
read or write buffering or a faster, high performance
interface can be designed to communicate with the R4650.
Again, the system designer has the flexibility to make these
price/performance trade-offs.
System Command Bus
The R4650 interface has a 9-bit System Command
(SysCmd) bus. The command bus indicates whether the
SysAD bus carries an address or data. If the SysAD carries
an address, then the SysCmd bus also indicates what type
of transaction is to take place (for example, a read or write).
If the SysAD carries data, then the SysCmd bus also gives
information about the data (for example, this is the last data
word transmitted, or the cache state of this data line is
clean exclusive). The SysCmd bus is bidirectional to
support both processor requests and external requests to
the R4650. Processor requests are initiated by the R4650
and responded to by an external device. External requests
are issued by an external device and require the R4650 to
respond.
MasterClock
SysAD
SysCmd
ValidOut
ValidIn
RdRdy
WrRdy
Release
Addr
Read
Data0 Data1
CData CData
Data2 Data3
CData CEOD
Figure 5: R4650 Block Read Request (64-bit interface option)
5.8
8
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