KE5BCCA4NCBP-A View Datasheet(PDF) - KAWASAKI MICROELECTRONICS

Part Name

Description

Manufacturer

KE5BCCA4NCBP-A

4,7M Classification CAM

KAWASAKI MICROELECTRONICS 

Kawasaki LSI

4.7M Classification CAM

PRELIMINARY

1. Features

The KE5BCCA4M is a high-performance Content Addressable Memory (CAM). The following

features enable high-speed and high-density “switching," “address filtering,” and "packet

classification" applications required for internetworking switching and routing:

• Density: 4.7Mbits Ternary or Binary

• Configurable table Size: 72-bit x 64k, 144-bit x 32k, 288-bit x 16k (Ternary or Binary)

• Mixed table size configuration:

Selected by each bank (8banks). Each bank can be individually configured as a 72-bit x 8K,

144-bit x 4K, or 288-bit x 2K (Ternary or Binary) table.

• Input Clock rate:

High-speed input mode: Double Data Rate

- Single rate clock mode: 100/83/66/50 MHz clock (CLK) and phase (PHASE)

- Double rate clock mode: 200/166/133/100MHz clock (CLK) and the half rate phase (PHASE)

Normal input mode: Single Data Rate with 100/83/66/50 MHz clock (CLK) and no phase signal

• High-speed search and deterministic latency:

-100: Sustained 100MLPS, 10ns per 144-bit maximum, 5 Cycles latency

-83: Sustained 83MLPS, 12ns per 144-bit maximum, 5 Cycles latency

-66: Sustained 66MLPS, 15ns per 144-bit maximum, 4 Cycles latency

-50: Sustained 50MLPS, 20ns per 144-bit maximum, 3 Cycles latency

• Dual-port architecture

• 72-bit I/O Port Data Bus:

144-bit per 10/12/15/20ns write-in throughput is possible in the high-speed input mode. 72-bit

I/O port data bus is also configurable as a 40-bit wide bus.

• 23-bit Output Port: Search results are output

• Multi-hit support (Highest Hit Address output)

• 18 x 72-bit Global MASK Registers

• Weighted Search without data sorting:

-100: N/A

-83: 13.8Mpps (32-bit), 11.9Mpps (64-bit), 5.2Mpps (128-bit)

-66: 11.0Mpps (32-bit), 9.4Mpps (64-bit), 4.1Mpps (128-bit)

-50: 8.3Mpps (32-bit), 7.1Mpps (64-bit), 3.1Mpps (128-bit)

Note: When data sorting is done in advance, the look up rate is 100/83/66/50Mpps respectively.

• Effective Command Set for Table Management:

- Purge (Invalidate) all the hit entries in one Cycle

- Automatic Learning

• Cascading:

Up to 8pcs --- Glueless without degradation in performance --- 72-bit x 512k table

Cascadable up to 32pcs --- Maximum 72-bit x 2M table

• External SRAM direct connection (Address bypass to SRAM)

• Space-saving package: 324-pin BGA (27mm x 27mm)

• Power supply: ‘1.8V(core) and 1.8V(I/O)’, or ‘1.8V(core) and 2.5V/3.3V(I/O)’

Version 2.3.8

1

Confidential

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