KE5BCCA4MCBP-E View Datasheet(PDF) - KAWASAKI MICROELECTRONICS

Part Name

Description

Manufacturer

KE5BCCA4MCBP-E

4,7M Classification CAM

KAWASAKI MICROELECTRONICS 

Kawasaki LSI

4.7M Classification CAM

PRELIMINARY

4. Functional Descriptions

4.1. Overview

KE5BCCA4M has a dual-port architecture: I/O port and Output port. The I/O port is for search key

data input and command input. The output port is for the search result output.

Commands are asserted through the CNTL [13:0] bus. Read/write of stored data and search key

data are provided through DAT[63:0] and EDAT[7:0]. This 72-bit bus (DAT[63:0] and EDAT[7:0]) can

be defined as 72-bit or 40-bit.

The CAM table consists of 8 banks, each of which can be configured as Ternary and Binary and in

table widths of 72-bit, 144-bit or 288-bit. The search operation can be performed simultaneously on

multiple banks of the same configuration.

The CAM also provides the function called Weighted Search without data sorting. That is,

regardless of the order of the data stored, the most weighted entry is output when a search

operation results in multiple hit.

4.2. Segment Structure

Extra 8bits

Data 64bits

71

64 63

Local Data

Local Mask Data

0

Empty Hit

Bit

Flag

4.3. Output Format

Classification

CAM

22 21 20

16 15

0

OD[22:0]

DEVID[4:0]

HHA/HEA[15:0]

SSHON

SMON

Device ID[4:0]

HHA/HEA Flag (0:HHA, 1:HEA)

Valid Flag (0:Valid, 1:Invalid)

OEODN

Version 2.3.8

7

Confidential

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