T2080NSE8PTB View Datasheet(PDF) - NXP Semiconductors.
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Description
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T2080NSE8PTB Datasheet PDF : 186 Pages
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NXP Semiconductors
Data Sheet: Technical Data
QorIQ T2080 Data Sheet
Features
• 4 e6500 cores built on Power Architecture®
technology sharing a 2 MB L2 cache
• 512 KB CoreNet platform cache (CPC)
• Hierarchical interconnect fabric
– CoreNet fabric supporting coherent and non-
coherent transactions with prioritization and
bandwidth allocation amongst CoreNet end-points
– Queue Manager (QMan) fabric supporting packet-
level queue management and quality of service
scheduling
• One 32-/64-bit DDR3 SDRAM memory controller
– DDR3 and DDR3L with ECC and interleaving
support
– Memory pre-fetch engine
• Data Path Acceleration Architecture (DPAA)
incorporating acceleration for the following functions:
– Packet parsing, classification, and distribution
(Frame Manager 1.1)
– Queue management for scheduling, packet
sequencing, and congestion management (Queue
Manager 1.1)
– Hardware buffer management for buffer allocation
and de-allocation (Buffer Manager 1.1)
– Cryptography Acceleration (SEC 5.2)
– RegEx Pattern Matching Acceleration (PME 2.1)
– Decompression/Compression Acceleration (DCE
1.0)
– DPAA chip-to-chip interconnect via RapidIO
Message Manager (RMan 1.0)
Document Number T2080
Rev. 3, 03/2018
T2080
• 16 SerDes lanes at up to 10 GBaud
• 8 Ethernet interfaces, supporting combinations of:
– Up to four 10 Gbps Ethernet MACs
– Up to eight 1 Gbps Ethernet MACs
– Up to four 2.5Gbps Ethernet MACs
– IEEE Std 1588™ support
• High-speed peripheral interfaces
– Four PCI Express controllers (two support PCIe 2.0
and two support PCIe 3.0)
– Two Serial RapidIO 2.0 controllers running at up to
5 GBaud with Type 11 messaging and Type 9 data
streaming support
• Additional peripheral interfaces
– Two Serial ATA (SATA 2.0) controllers
– Two high-speed USB 2.0 controllers with integrated
PHY
– Enhanced secure digital host controller (SD/MMC/
eMMC)
– Enhanced Serial peripheral interface (eSPI)
– Four I2C controllers
– Four 2-pin UARTs or two 4-pin UARTs
– Integrated flash controller supporting NAND and
NOR flash
• Three 8-channel DMA engines
• 896 FC-PBGA package, 25 mm x 25 mm, 0.8mm pitch
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
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