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ST7LITE39 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
ST7LITE39 Datasheet PDF : 167 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Table 2. Hardware Register Map
Address Block
Register
Label
Register Name
0000h
0001h
0002h
Port A
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
0003h
0004h
0005h
Port B
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
0006h
0007h
Reserved area (2 bytes)
0008h
0009h
000Ah
000Bh
000Ch
LITE
TIMER 2
LTCSR2
LTARR
LTCNTR
LTCSR1
LTICR
Lite Timer Control/Status Register 2
Lite Timer Auto-reload Register
Lite Timer Counter Register
Lite Timer Control/Status Register 1
Lite Timer Input Capture Register
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
AUTO-
RELOAD
TIMER 3
ATCSR
CNTR1H
CNTR1L
ATR1H
ATR1L
PWMCR
PWM0CSR
PWM1CSR
PWM2CSR
PWM3CSR
DCR0H
DCR0L
DCR1H
DCR1L
DCR2H
DCR2L
DCR3H
DCR3L
ATICRH
ATICRL
ATCSR2
BREAKCR
ATR2H
ATR2L
DTGR
Timer Control/Status Register
Counter Register 1 High
Counter Register 1 Low
Auto-Reload Register 1 High
Auto-Reload Register 1 Low
PWM Output Control Register
PWM 0 Control/Status Register
PWM 1 Control/Status Register
PWM 2 Control/Status Register
PWM 3 Control/Status Register
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
PWM 1 Duty Cycle Register High
PWM 1 Duty Cycle Register Low
PWM 2 Duty Cycle Register High
PWM 2 Duty Cycle Register Low
PWM 3 Duty Cycle Register High
PWM 3 Duty Cycle Register Low
Input Capture Register High
Input Capture Register Low
Timer Control/Status Register 2
Break Control Register
Auto-Reload Register 2 High
Auto-Reload Register 2 Low
Dead Time Generator Register
0026h to
002Dh
Reserved area (8 bytes)
002Eh
WDG WDGCR
Watchdog Control Register
0002Fh FLASH FCSR
Flash Control/Status Register
00030h EEPROM EECSR
Data EEPROM Control/Status Register
ST7LITE3
Reset Status Remarks
FFh1)
00h
40h
FFh 1)
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W2)
0Fh
00h
00h
0X00 0000h
xxh
0X00 0000h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
03h
00h
00h
00h
00h
R/W
R/W
Read Only
R/W
Read Only
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
7Fh
R/W
00h
R/W
00h
R/W
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