TX4925 View Datasheet(PDF) - Toshiba
Part Name
Description
Manufacturer
TX4925 Datasheet PDF : 32 Pages
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INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE
DMA Interface
Signal Name
DMAREQ [1:0]
DMAACK [1:0]
DMADONE*
Type
Input
PU
Output
Input/out
put
PU
Function
DMA Request
DMA transfer request signals from an external I/O device.
The pins are shared with other functions.
DMA Acknowledge
DMA transfer acknowledge signals to an external I/O device.
The pins are shared with other functions.
DMA Done
DMADONE* is either used as an output signal that reports the termination of DMA
transfer or as an input signal that causes DMA transfer to terminate.
The pin is shared with other functions.
Initial State
PIO input
PIO input
PIO input
PCI Interface
Signal Name
PCICLK [2:1]
PCICLKIO
PCIAD [31:0]
C_BE [3:0]
PAR
FRAME*
IRDY *
TRDY *
STOP*
Type
Output
Input/out
put
Input/out
put
Input/out
put
Input/out
put
Input/out
put
Input/out
put
Input/out
put
Input/out
put
Function
Initial State
PCI Clock
PCI bus clock signals.
A boot configuration signal (ADDR[18]) can determine whether the clock internally
generated in the TX4925 is used as PCICLK. If the TX4925 internal clock is selected,
the clock signals are output from these pins.
Selected
by
ADDR[18]
H: High
L: L
When these clock signals are not used, the pins can be set to Hi-Z using the
PCICLK Enable field of the pin configuration register (PCFG.PCICLKEN[2:1]).
PCI Feedback Clock
PCI feedback clock input.
A boot configuration signal (ADDR[18]) can determine whether the clock internally
generated in the TX4925 is used as PCICLK. If the TX4925 internal clock is selected,
the clock signals are output and simultaneously fed back to the internal PCI block.
When using the PCI block, therefore, do not set the PCICLK Enable field of the pin
configuration register (PCFG.PCICLKIOEN) to 0.
Selected
by
ADDR[18]
H: High
L: Input
PCI Address and Data
Multiplexed address and data bus.
Input
Command and Byte Enable
Command and byte enable signals.
Input
Parity
Input
Even parity signal for PCIAD[31:0] and C_BE[3:0]*.
Cycle Frame
Indicates that bus operation is in progress.
Input
Initiator Ready
Indicates that the initiator is ready to complete data transfer.
Input
Target Ready
Input
Indicates that the target is ready to complete data transfer.
Stop
The target sends this signal to the initiator to request termination of data transfer.
Input
EJC-TMPR4925XB -19
26/Dec/01 Rev 0.1
TOSHIBA CORPORATION
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