TX4925 View Datasheet(PDF) - Toshiba

Part Name

Description

Manufacturer

TX4925

64-bit RISC MICROPROCESSOR

Toshiba 

INTEGRATED CIRCUIT

TOSHIBA RISC PROCESSOR

TMPR4925XB

TENTATIVE

2.3 TX49/H2 Core Block Diagram

Figure 3 shows the internal block diagram of the TX49/H2 core

TX49/H2 Core

Integer Unit

CP0

CP0 Registers

GPR

MMU/TLB

Data Pipeline

Path Control

Exception Unit

MAC

CP1

FPU

Debug

Support

Unit

16KB

4-way set

Instruction

Cache

Write

Buffer

16KB

4-way set

Data

Cache

Figure 2.3 TX49/H2 Core Block Diagram

2.4 TX49/H2 CORE FEATURES

The TX49/H2 Core is high performance and low-power 64-bit RISC processor core

developed by Toshiba.

• 64-bit operation

• 32, 64-bit integer general purpose registers

• 32-bit physical address space and 64-bit virtual address space

• Optimized 5-stage pipeline

• Instruction Set

MIPS I, II , III compatible ISA

PREF (Prefetch) and MAC (Multiply/Accumulate) instructions.

• 16k Byte Instruction Cache, and 16k Byte Data Cache

4-way set associative with lock function

• MMU (Memory Management Unit): 48-entry fully associative JTLB

• The on-chip FPU supports both single- and double-precision arithmetic, as specified in

IEEE Std 754.

• On-chip 4-deep write buffer

• Enhanced JTAG debug feature

Built-in Debug Support Unit (DSU)

EJC-TMPR4925XB -4

26/Dec/01 Rev 0.1

TOSHIBA CORPORATION

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