CY62138V(1998) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY62138V Datasheet PDF : 9 Pages
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PRELIMINARY
CY62138V MoBL™
Features
• Low voltage range:
— 1.8−3.3V
• Ultra-low active power
• Low standby power
• Easy memory expansion with CS1/CS2 and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62138V is a high-performance CMOS static RAM or-
ganized as 262,144 words by 8 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
The device can be put into standby mode when deselected
(CS1 HIGH or CS2 LOW).
256K x 8 Static RAM
Writing to the device is accomplished by taking chip enable
one (CS1) and write enable (WE) inputs LOW and chip enable
two (CS2) input HIGH. Data on the eight I/O pins (I/O0 through
I/O7) is then written into the location specified on the address
pins (A0 through A17).
Reading from the device is accomplished by taking chip en-
able one (CS1) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CS2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CS1
HIGH or CS2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CS1 LOW, CS2 HIGH, and WE LOW).
The 62138V MoBL SRAM has an extremely wide operating
voltage range. The datasheet has been specified to accurately
describe the device behavior at three common voltage ranges
(3.3−2.7, 2.7−2.3, 2.3−1.8)
The CY62138V is available in a 36-ball FBGA.
Logic Block Diagram
A0
A1
A2
AA34
AA56
A7
A8
CCSS21
WE
OE
Data in Drivers
256K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
62138V-1
Pin Configuration
FBGA
TOP View
1
2
34
56
A 0 A1 CS2 A3 A6 A8
A
I/O4 A2 WE A4 A7 I/O0
B
I/O5
NC A5
I/O1
C
VSS
VCC
D
VCC
VSS
E
I/O6
NC A17
I/O2
F
I/O7 OE CS1 A16 A15 I/O4
G
A9
A10 A11 A12 A13 A14
H
62138V–2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 1998
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