CY62138V(1998) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY62138V Datasheet PDF : 9 Pages
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PRELIMINARY
CY62138V MoBL™
Switching Characteristics Over the Operating Range[4]
Parameter
Description
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[5]
OE HIGH to High Z[5, 6]
CE LOW to Low Z[5]
CE HIGH to High Z[5, 6]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
WRITE CYCLE[7 ,8]
tWC
Write Cycle Time
tSCE
CE LOW to Write End
tAW
Address Set-Up to Write End
tHA
Address Hold from Write End
tSA
Address Set-Up to Write Start
tPWE
WE Pulse Width
tSD
Data Set-Up to Write End
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High Z[ 5, 6]
WE HIGH to Low Z[5]
Shaded area contains advanced information.
(2.7V−3.3V
Operation)
Min. Max.
70
70
10
70
35
5
25
10
25
0
70
70
60
60
0
0
50
30
0
25
10
Switching Waveforms
Read Cycle No. 1[9,10]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
(2.3V−2.7V
Operation)
Min. Max.
(1.8V−2.3V
Operation)
Min. Max.
85
100
85
100
10
10
85
100
50
75
5
5
35
50
10
10
35
50
0
0
85
100
85
100
75
90
75
90
0
0
0
0
65
80
50
60
0
0
35
50
10
10
DATA VALID
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C62256–8
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC typ., and output loading of the
specified IOL/IOH and 30 pF load capacitance.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
8. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
9. Device is continuously selected. OE, CE = VIL.
10. WE is HIGH for read cycle.
5
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