CY7C1031-7JC View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY7C1031-7JC

64K x 18 Synchronous Cache RAM

Cypress Semiconductor 

PRELIMINARY

CY7C1031

CY7C1032

66–MHz OSC

CLK

ADR

DATA

ADS

PENTIUM

PROCESSOR

CLK

ADR

CD

CACHE DATA

TAG

MATCH

DIRTY

VALID

512 KB

CLK

ADR

DATA

ADSP

ADSC

ADV

OE

7C1031

WH, WL

WH, WL WH, WL

WH, WL

2

2

CLK ADSC

ADR

DATA

ADSP

ADV OE WH0,

WL0

CACHE

CONTROLLER

WH1,

WL1

MATCH

DIRTY

VALID

2

WH2,

WL2

2

WH3,

WL3

Figure 1. Cache Using Four CY7C1031s

INTERFACE TO

MAIN MEMORY

Pin Definitions

Signal Name

VCC

VCCQ

GND

VSSQ

CLK

A15 – A0

ADSP

ADSC

WH

WL

ADV

OE

CS

DQ15–DQ0

DP1–DP0

Type

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input/Output

Input/Output

# of Pins

1

4

1

4

1

16

1

1

1

1

1

1

1

16

2

Description

+5V Power

+5V or 3.3V (Outputs)

Ground

Ground (Outputs)

Clock

Address

Address Strobe from Processor

Address Strobe from Cache Controller

Write Enable – High Byte

Write Enable – Low Byte

Advance

Output Enable

Chip Select

Regular Data

Parity Data

3

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