CY7C1031-7JC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1031-7JC Datasheet PDF : 14 Pages
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PRELIMINARY
CY7C1031
CY7C1032
Pin Descriptions
Signal
Name I/O
Description
Input Signals
CLK
I Clock signal. It is used to capture the address,
the data to be written, and the following control
signals: ADSP, ADSC, CS, WH, WL, and ADV. It
is also used to advance the on-chip auto-ad-
dress-increment logic (when the appropriate
control signals have been set).
A15–A0
I
Sixteen address lines used to select one of 64K
locations. They are captured in an on-chip regis-
ter on the rising edge of CLK if ADSP or ADSC
is LOW. The rising edge of the clock also loads
the lower two address lines, A1 – A0, into the
on-chip auto-address-increment logic if ADSP or
ADSC is LOW.
ADSP
I Address strobe from processor. This signal is
sampled at the rising edge of CLK. When this
input and/or ADSC is asserted, A0–A15 will be
captured in the on-chip address register. It also
allows the lower two address bits to be loaded
into the on-chip auto-address-increment logic. If
both ADSP and ADSC are asserted at the rising
edge of CLK, only ADSP will be recognized. The
ADSP input should be connected to the ADS out-
put of the processor. ADSP is ignored when CS
is HIGH.
ADSC
I Address strobe from cache controller. This signal
is sampled at the rising edge of CLK. When this
input and/or ADSP is asserted, A0–A15 will be
captured in the on-chip address register. It also
allows the lower two address bits to be loaded
into the on-chip auto-address-increment logic.
The ADSC input should not be connected to the
ADS output of the processor.
WH
I Write signal for the high-order half of the RAM
array. This signal is sampled by the rising edge
of CLK. If WH is sampled as LOW, i.e., asserted,
the control logic will perform a self-timed write of
DQ15 – DQ8 and DP1 from the on-chip data reg-
ister into the selected RAM location. There is one
exception to this. If ADSP, WH, and CS are as-
serted (LOW) at the rising edge of CLK, the write
signal, WH, is ignored. Note that ADSP has no
effect on WH if CS is HIGH.
WL
I Write signal for the low-order half of the RAM
array. This signal is sampled by the rising edge
of CLK. If WL is sampled as LOW, i.e., asserted,
the control logic will perform a self-timed write of
DQ7 – DQ0 and DP0 from the on-chip data reg-
ister into the selected RAM location. There is one
exception to this. If ADSP, WL, and CS are as-
serted (LOW) at the rising edge of CLK, the write
signal, WL, is ignored. Note that ADSP has no
effect on WL if CS is HIGH.
Pin Descriptions (continued)
Signal
Name I/O
Description
ADV
I Advance. This signal is sampled by the rising
edge of CLK. When it is asserted, it automatically
increments the 2-bit on-chip auto-address-incre-
ment counter. In the CY7C1032, the address will
be incremented linearly. In the CY7C1031, the
address will be incremented according to the
Pentium/486 burst sequence. This signal is ig-
nored if ADSP or ADSC is asserted concurrently
with CS. Note that ADSP has no effect on ADV
if CS is HIGH.
CS
I Chip select. This signal is sampled by the rising
edge of CLK. If CS is HIGH and ADSC is LOW,
the SRAM is deselected. If CS is LOW and ADSC
or ADSP is LOW, a new address is captured by
the address register. If CS is HIGH, ADSP is ig-
nored.
OE
I Output enable. This signal is an asynchronous
input that controls the direction of the data I/O
pins. If OE is asserted (LOW), the data pins are
outputs, and the SRAM can be read (as long as
CS was asserted when it was sampled at the
beginning of the cycle). If OE is deasserted
(HIGH), the data I/O pins will be three-stated,
functioning as inputs, and the SRAM can be writ-
ten.
Bidirectional Signals
DQ15–DQ0 I/O
Sixteen bidirectional data I/O lines. DQ15 – DQ8
are inputs to and outputs from the high-order half
of the RAM array, while DQ7 – DQ0 are inputs to
and outputs from the low-order half of the RAM
array. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of
CLK. As outputs, they carry the data read from
the selected location in the RAM array. The di-
rection of the data pins is controlled by OE: when
OE is high, the data pins are three-stated and
can be used as inputs; when OE is low, the data
pins are driven by the output buffers and are out-
puts. DQ15 – DQ8 and DQ7 – DQ0 are also
three-stated when WH and WL, respectively, is
sampled LOW at clock rise.
DP1–DP0 I/O Two bidirectional data I/O lines. These operate
in exactly the same manner as DQ15 – DQ0, but
are named differently because their primary pur-
pose is to store parity bits, while the DQs’ primary
purpose is to store ordinary data bits. DP1 is an
input to and an output from the high-order half of
the RAM array, while DP0 is an input to and an
output from the lower-order half of the RAM ar-
ray.
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