LH28F008SC Datasheet PDF - Sharp Electronics

LH28F008SC View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F008SC

8M (1M × 8) Flash Memory

Sharp Electronics

LH28F008SC Datasheet PDF : 38 Pages

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8M (1M × 8) Flash Memory

LH28F008SC

The RY »/BY » output gives an additional indicator of

WSM activity by providing both a hardware signal of

status (versus software polling) and status masking

(interrupt masking for background block erase, for

example). Status polling using RY »/BY » minimizes both

CPU overhead and system power consumption. When

low, RY/» BY» indicates that theWSM is performing a block

erase, byte write, or lock-bit configuration. RY »/BY » high

indicates that the WSM is ready for a new command,

block erase is suspended (and byte write is inactive),

byte write is suspended, or the device is in deep power-

down mode.

The access time is 85 ns (tAVAV) over the commer-

cial temperature range (0°C to +70°C) and VCC supply

voltage range of 4.75 V - 5.25 V. At lower VCC voltages,

the access times are 90 ns (4.5 V - 5.5 V) and 120 ns

(3.0 V - 3.6 V).

The Automatic Power Savings (APS) feature substan-

tially reduces active current when the device is in static

mode (addresses not switching). In APS mode, the typi-

cal ICCR current is 1 mA at 5 V VCC.

When CE » and RP » pins are at VCC, the ICC CMOS

standby mode is enabled. When the RP » pin is at GND,

deep power-down mode is enabled which minimizes

power consumption and provides write protection dur-

ing reset. A reset time (tPHQV) is required from RP »

switching high until outputs are valid. Likewise, the de-

vice has a wake time (tPHEL) from RP »-high until writes

to the CUI are recognized. With RP » at GND, the WSM

is reset and the status register is cleared.

The device is available in 40-pin TSOP (Thin Small

Outline Package, 1.2 mm thick) and 44-pin SOP (Small

Outline Package). Pinouts are shown in Figures 1 and 2.

PRINCIPLES OF OPERATION

The LH28F008SC SmartVoltage FlashFile memory

includes an on-chip WSM to manage block erase, byte

write, and lock-bit configuration functions. It allows for:

100% TTL-level control inputs, fixed power supplies dur-

ing block erasure, byte write, and lock-bit configuration,

and minimal processor overhead with RAM-like inter-

face timings.

After initial device power-up or return from deep

power-down mode (see Bus Operations), the device

defaults to read array mode. Manipulation of external

memory control pins allow array read, standby, and out-

put disable operations.

Status register and identifier codes can be accessed

through the CUI independent of the VPP voltage. High

voltage on VPP enables successful block erasure, byte

writing, and lock-bit configuration. All functions associ-

ated with altering memory contents–block erase, byte

write, Lock-bit configuration, status, and identifier codes-

are accessed via the CUI and verified through the sta-

tus register.

Commands are written using standard microproces-

sor write timings. The CUI contents serve as input to

the WSM, which controls the block erase, byte write,

and lock-bit configuration. The internal algorithms are

regulated by the WSM, including pulse repetition, inter-

nal verification, and margining of data. Addresses and

data are internally latch during write cycles. Writing the

appropriate command outputs array data, accesses the

identifier codes, or outputs status register data.

Interface software that initiates and polls progress of

block erase, byte write, and lock-bit configuration can

be stored in any block. This code is copied to and ex-

ecuted from system RAM during flash memory updates.

After successful completion, reads are again possible

via the Read Array command. Block erase suspend al-

lows sytem software to suspend a block. Byte write sus-

pend allows system software to suspend a byte write to

read data from any other flash memory array location.

FFFFF

F0000

EFFFF

E0000

DFFFF

D0000

CFFFF

C0000

BFFFF

B0000

AFFFF

A0000

9FFFF

90000

8FFFF

80000

7FFFF

70000

6FFFF

60000

5FFFF

50000

4FFFF

40000

3FFFF

30000

2FFFF

20000

1FFFF

10000

0FFFF

00000

64KB BLOCK

Figure 4. Memory Map

28F008SC-4

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