LH28F008SC View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F008SC

8M (1M × 8) Flash Memory

Sharp Electronics 

LH28F008SC

8M (1M × 8) Flash Memory

Data Protection

Depending on the application, the system designer

may choose to make the VPP power supply switchable

(available only when memory block erases, byte writes,

or lock-bit configurations are required) or hardwired to

VPPH1/2/3. The device accommodates either design prac-

tice and encourages optimization of the processor-

memory interface.

When VPP ≤ VPPLK, memory contents cannot be

altered. The CUI, with two-step block erase, byte write,

or lock-bit configuration command sequences, provides

protection from unwanted operations even when high

voltage is applied toVPP. All write functions are disabled

when VCC is below the write lockout voltage VLKO or

when RP » is at VIL. The device’s block locking capability

provides additional protection from inadvertent code or

data alteration by gating erase and byte write

operations.

BUS OPERATION

The local CPU reads and writes flash memory

in-system. All bus cycles to or from the flash memory

conform to standard microprocessor bus cycles.

Read

Information can be read from any block, identifier

codes, or status register independent of the VPP volt-

age. RP » can be at either VIH or VHH.

The first task is to write the appropriate read mode

command (Read, Array, Read Identifier Codes, or Read

Status Register) to the CUI. Upon initial device power-

up or after exit from deep power-down mode, the de-

vice automatically resets to read array mode. Four

control pins dictate the data flow in and out of the com-

ponent: CE », OE », WE », and RP ». CE » and OE » must be

driven active to obtain data at the outputs. CE » is the

device selection control, and when active enables the

selected memory device. OE » is the data output

(DQ0 - DQ7) control and when active drives the selected

memory data onto the I/O bus. WE » must be at VIH and

RP » must be at VIH or VHH. Figure 15 illustrates a read

cycle.

Output Disable

With OE » at a logic-high level (VIH), the device otuputs

are disabled. Output pins DQ0 - DQ7 are placed in a

high-impedance state.

Standby

CE » at a logic-high level (VIH) places the device in

standby mode which substantially reduces device power

consumption. DQ0 - DQ7 outputs are placed in a high-

impedance state independent of OE .» If deselected dur-

ing block erase, byte write, or lock-bit configuration, the

device continues functioning, and consuming

active power until the operation completes.

Deep Power-Down

RP » at VIL initiates the deep power-down mode.

In read modes, RP-» low deselects the memory, places

output drivers in a high-impedance state and turns off

all internal circuits. RP » must be held low for a minimum

of 100 ns.Time tPHQV is required after return from power-

down until initial memory access outputs are valid. Af-

ter this wake-up interval, normal operation is restored.

The CUI is reset to read array mode and status register

is set to 80H.

During block erase, byte write, or lock-bit configura-

tion modes, RP »-low will abort the operation. RY »/BY »

remains low until the reset operation is complete.

Memory contents being altered are no longer valid; the

data may be partially erased or written. Time tPHWL is

required after RP » goes to logic-high (VIH) before an-

other command can be written.

As with any automated device, it is important to

assert RP» during system reset.When the system comes

out of reset, it expects to read from the flash memory.

Automated flash memories provide status information

when accessed during block erase, byte write, or lock-

bit configuration modes. If a CPU reset occurs with no

flash memory reset, proper CPU initialization may not

occur because the flash memory may be providing sta-

tus information instead of array data. SHARP’s flash

memories allow proper CPU initialization following a

system reset through the use of the RP » input. In this

application, RP » is controlled by the same RESET sig-

nal that resets the system CPU.

Read Identifier Codes Operation

The read identifier codes operation outputs the manu-

facturer code, device code, block lock configuration

codes for each block, and the master lock configuration

code (see Figure 5). Using the manufacturer and de-

vice codes, the system CPU can automatically match

the device with its proper algorithms. The block lock and

master lock configuration codes identify locked and

unlocked blocks and master lock-bit setting.

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