LTC2912CTS81-TRMPBF View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
LTC2912CTS81-TRMPBF Datasheet PDF : 14 Pages
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LTC2912
TYPICAL PERFORMANCE CHARACTERISTICS
UV Output Voltage vs VCC
5
VH = 0.55V
SEL = VCC
4
3
2
1
0
0
1
2
3
4
5
SUPPLY VOLTAGE, VCC (V)
2912 G07
UV/OV, Voltage Output Low
vs Output Sink Current
1.0
85°C
25°C
0.8
–40°C
0.6
0.4
0.2
0
0
5 10 15 20 25 30
IUV/OV (mA)
1912 G10
Reset Time-Out Period
vs Capacitance
10000
1000
100
10
1
0.1
1
10
100
1000
TMR PIN CAPACITANCE, CTMR (nF)
2912 G08
Reset Timeout Period
vs Temperature
12
CTMR = 1nF
11
10
9
8
7
6
–50 –25 0
25 50
TEMPERATURE (°C)
75 100
2912 G11
UV, ISINK vs VCC
5
VH = 0.45V
SEL = VCC
4
UV AT 150mV
3
2
UV AT 50mV
1
0
0
1
2
3
4
5
SUPPLY VOLTAGE, VCC (V)
2912 G09
OV/OV Output Voltage vs VCC
5
VL = 0.55V
4
3
OV
2
OV
1
0
0
1
2
3
4
5
SUPPLY VOLTAGE, VCC (V)
2912 G12
PIN FUNCTIONS (DFN/TSOT Packages)
DIS (Pin 8/Pin 1, LTC2912-2): Output Disable Input.
Disables the OV and UV output pins. When DIS is pulled
high, the OV and UV pins are not asserted except during a
UVLO condition. Pin has a weak (2µA) internal pull-down
to GND. Leave pin open if unused.
Exposed Pad (Pin 9, DDB Package): Exposed Pad may
be left open or connected to device ground.
GND (Pin 5/Pin 4): Device Ground.
is cleared. While held high, OV/OV has a similar delay and
output characteristic as UV.
OV (Pin 6/Pin 3, LTC2912-1, LTC2912-2): Overvoltage
Logic Output. Asserts low when the VL input voltage is
above threshold. Latched low (LTC2912-1). Held low for
programmed delay time after VL input is valid (LTC2912-
2). Pin has a weak pull-up to VCC and may be pulled above
VCC using an external pull-up. Leave pin open if unused.
LATCH (Pin 8/Pin 1, LTC2912-1, LTC2912-3): OV/OV
Latch Clear/Bypass Input. When pulled high, OV/OV latch
Rev. C
6
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