CL7160E and CL7160S Laser Processed Logic Devices
AC Test Conditions
(A)
VCCIO
464 Ω
OUTPUT
35 pF
Includes jig
capacitance
250 Ω
(B)
VCCIO
464 Ω
OUTPUT
5 pF
Includes jig
capacitance
250 Ω
All Input Pulses
3.0V
90%
90%
GND 10%
≤ 3ns
10%
≤ 3ns
7K drw 02A
Notes to Tables
1. During transitions, inputs may undershoot to -2.0V for periods shorter than
20ns. Otherwise, minimum DC input voltage is 0.3V.
2. Typical values are at VCC of 5.0 volts and ambient temperature of 25 ºC.
3. Guaranteed but not tested. Characterized initially, and after any design
changes which may affect these parameters.
4. Internal timing delays are based on characterization, and cannot be explicitly
tested. Internal timing parameters should be used for performance estimation
only.
Revision History
11 Jan. 1999:
30 Apr. 1999:
31 July 1999:
13 Oct. 1999:
1 Dec. 2000:
Created new document
Recompiled databook, no changes.
Added -6ns speed grade, revised the Product Family Overview,
corrected Pin Configuration Table
Corrected typographical error in AC Test Condition diagram (W
changed to W)
Updated application note reference.
Page 13